參數(shù)資料
型號: MAX4657ESA+T
廠商: Maxim Integrated Products
文件頁數(shù): 10/12頁
文件大?。?/td> 0K
描述: IC SWITCH SPST 8SOIC
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
功能: 開關
電路: 1 x SPST- NC
導通狀態(tài)電阻: 10 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 9 V ~ 40 V,±4.5 V ~ 20 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOIC
包裝: 帶卷 (TR)
Detailed Description
The MAX4655–MAX4658 are single SPST CMOS ana-
log switches. The CMOS switch construction provides
rail-to-rail signal handling while consuming very little
power. The switch is controlled by a TTL/CMOS level
compatible digital input. The MAX4655/MAX4657 are
normally closed switches, and the MAX4656/MAX4658
are normally open switches.
These devices can be operated with either single
power supplies or dual power supplies. Operation at up
to ±20V supplies allows users a wide switching dynamic
range. Additionally, asymmetrical operation is possible
to tailor performance to a particular application.
These switches have been specifically designed to
handle high switch currents, up to 400mA peak current
and 300mA continuous currents. In order to do this, a
new technique is used to drive the body of the output
N-channel device. (Note: the basic switch between the
input NC/NO terminal, and the output common terminal
consists of an N-channel MOSFET and a P-channel
MOSFET in parallel.) The standard method limits opera-
tion to approximately a 600mV drop across the switch.
More than 600mV causes an increase in IdON leakage
current (due to the turn-on of on-chip parasitic diodes)
and an increase in V+ supply current. With the new
sensing method, there is no limitation to the voltage
drop across the switch. Current and voltage are limited
only by the power dissipation rating of the package and
the absolute maximum ratings of the switch.
When the analog input to output voltage drop is
approximately 7mV there is an increase in power sup-
ply current from typically 90A to 2mA within a 1mV to
7mV range, caused by the new sensing/driving circuitry.
Applications Information
Overvoltage Protection
Proper power-supply sequencing is recommended for
all CMOS devices. Do not exceed the absolute maxi-
mum ratings, because stresses beyond the listed rat-
ings can cause permanent damage to the devices.
First, connect GND, followed by V+, V-, and the remain-
ing pins. If power-supply sequencing is not possible,
add two small signal diodes (D1, D2) in series with sup-
ply pins (Figure 1). Adding diodes reduces the analog
signal range to one diode drop below V+ and one
diode drop above V-, but does not affect the devices’
low switch resistance and low leakage characteristics.
Device operation is unchanged, and the difference
between V+ and V- should not exceed 44V. The protec-
tion diode for the negative supply is not required when
V- is connected to GND.
Off-Isolation at High Frequencies
In 50
Ω systems, the high-frequency on-response of
these parts extends from DC to above 100MHz, with a
typical loss of -2dB. When the switch is turned off, how-
ever, it behaves like a capacitor, and off-isolation
decreases with increasing frequency. This effect is
more pronounced with higher source and load imped-
ances. Above 5MHz, circuit board layout becomes
critical. The graphs shown in the Typical Operating
Characteristics were taken using a 50
Ω source and
load connected with BNC connectors.
MAX4655–MAX4658
High-Current, 10
Ω, SPST, CMOS
Analog Switches
_______________________________________________________________________________________
7
V+
COM_
V-
NO_
Vg
V+
V-
Figure 1. Overvoltage Protection Using Blocking Diodes
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