參數(shù)資料
型號: MAX4760ETX+
廠商: Maxim Integrated Products
文件頁數(shù): 13/14頁
文件大?。?/td> 0K
描述: IC SWITCH QUAD DPDT 36TQFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 50
功能: 開關
電路: 4 x DPDT
導通狀態(tài)電阻: 3.5 歐姆
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 1.8 V ~ 5.5 V
電流 - 電源: 10nA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-WFQFN 裸露焊盤
供應商設備封裝: 36-TQFN 裸露焊盤(6x6)
包裝: 管件
MAX4760/MAX4760A/MAX4761/MAX4761A
High-Bandwidth, Quad DPDT Switches
8
_______________________________________________________________________________________
Detailed Description
The MAX4760/MAX4760A quad double-pole/double-
throw (DPDT) and the MAX4761/MAX4761A octal sin-
gle-pole/double-throw (SPDT) analog switches operate
from a single +1.8V to +5.5V supply. These devices are
fully specified for +3V applications.
The MAX4760/MAX4760A/MAX4761/MAX4761A have a
guaranteed 2.0
Ω (typ) on-resistance to switch data or
audio signals. The low 54pF (typ) capacitance and 0.2ns
change in skew makes them ideal for data switching
applications. The MAX4760/MAX4760A have four logic
inputs to control two switches in pairs and the
MAX4761/MAX4761A have one logic control input and an
enable input (EN) to disable the switches.
Applications Information
Digital Control Inputs
The MAX4760/MAX4760A/MAX4761/MAX4761A logic
inputs accept up to +5.5V regardless of the supply volt-
age. For example, with a +3.3V supply, IN_ can be dri-
ven low to GND and high to +5.5V, which allows mixed
logic levels in a system. Driving the control logic inputs
rail-to-rail also minimizes power consumption.
For the MAX4761/MAX4761A, drive EN low to enable.
When EN is high, COM_ is high impedance.
Analog Signal Levels
Analog signal inputs over the full voltage range (0V to V+)
are passed through the switch with minimal change in on-
resistance (see the
Typical Operating Characteristics).
The switches are bidirectional so NO_, NC_, and COM_
can be either inputs or outputs.
Power-Supply Bypassing
Power-supply bypassing improves noise margin and
prevents switching noise from propagating from the V+
supply to other components. A 0.1F capacitor connect-
ed from V+ to GND is adequate for most applications.
Power-Supply Sequencing
CMOS devices require proper power-supply sequenc-
ing. Always apply V+ before the analog signals, espe-
cially if the input signal is not current limited. If
sequencing is not possible, and the input signal is not
current limited to less than 20mA, add a small-signal
diode (Figure 1). Adding the diode reduces the analog
range to a diode drop (0.7V) below V+ and increases
the on-resistance slightly. The maximum supply voltage
must not exceed +6V at any time.
UCSP Applications Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, printed circuit
board techniques, bump-pad layout, and recommend-
ed reflow temperature profile, as well as the latest infor-
mation on reliability testing results, refer to the
Application Note 1891:
Wafer-Level Packaging (WLP)
and Its Applications available on Maxim’s website at
www.maxim-ic.com/ucsp.
POSITIVE SUPPLY
COM
NO
D1
GND
V+
MAX4760
MAX4761
Figure 1. Overvoltage Protection Using an External Blocking
Diode
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