參數(shù)資料
型號: MAX492ESA+T
廠商: Maxim Integrated Products
文件頁數(shù): 7/17頁
文件大小: 0K
描述: IC OPAMP DUAL MICROPWR R/R 8SOIC
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
放大器類型: 通用
電路數(shù): 2
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 0.2 V/µs
增益帶寬積: 500kHz
電流 - 輸入偏壓: 25nA
電壓 - 輸入偏移: 200µV
電流 - 電源: 150µA
電流 - 輸出 / 通道: 30mA
電壓 - 電源,單路/雙路(±): 2.7 V ~ 6 V,±1.35 V ~ 3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
MAX492/MAX494/MAX495
Because the MAX492/MAX494/MAX495 have excellent
stability, no isolation resistor is required, except in the
most demanding applications. This is beneficial
because an isolation resistor would degrade the low-
frequency performance of the circuit.
Power-Up Settling Time
The MAX492/MAX494/MAX495 have a typical supply
current of 150A per op amp. Although supply current is
already low, it is sometimes desirable to reduce it further
by powering down the op amp and associated ICs for
periods of time. For example, when using a MAX494 to
buffer the inputs to a multi-channel analog-to-digital con-
verter (ADC), much of the circuitry could be powered
down between data samples to increase battery life. If
samples are taken infrequently, the op amps, along with
the ADC, may be powered down most of the time.
When power is reapplied to the MAX492/MAX494/
MAX495, it takes some time for the voltages on the sup-
ply pin and the output pin of the op amp to settle.
Supply settling time depends on the supply voltage, the
value of the bypass capacitor, the output impedance of
the incoming supply, and any lead resistance or induc-
tance between components. Op amp settling time
depends primarily on the output voltage and is slew-rate
limited. With the noninverting input to a voltage follower
held at mid-supply (Figure 10), when the supply steps
from 0V to VCC, the output settles in approximately 4s
for VCC = +3V (Figure 11a) or 10s for VCC = +5V
(Figure 11b).
Power Supplies and Layout
The MAX492/MAX494/MAX495 operate from a single
2.7V to 6V power supply, or from dual supplies of
±1.35V to ±3V. For single-supply operation, bypass the
power supply with a 1F capacitor in parallel with a
0.1F ceramic capacitor. If operating from dual sup-
plies, bypass each supply to ground.
Good layout improves performance by decreasing the
amount of stray capacitance at the op amp’s inputs and
output. To decrease stray capacitance, minimize both
trace lengths and resistor leads and place external
components close to the op amp’s pins.
Rail-to-Rail Buffers
The
Typical Operating Circuit shows a MAX495 gain-of-
two buffer driving the analog input to a MAX187 12-bit
ADC. Both devices run from a single 5V supply, and the
converter’s internal reference is 4.096V. The MAX495’s
typical input offset voltage is 200V. This results in an
error at the ADC input of 400V, or less than half of one
least significant bit (LSB). Without offset trimming, the
op amp contributes negligible error to the conversion
result.
Single/Dual/Quad, Micropower,
Single-Supply Rail-to-Rail Op Amps
14
______________________________________________________________________________________
VCC
1V/div
VOUT
500mV/div
5
s/div
VCC
2V/div
VOUT
1V/div
5
s/div
Figure 11b. Power-Up Settling Time (VCC = +5V)
Figure 11a. Power-Up Settling Time (VCC = +3V)
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