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參數(shù)資料
| 型號： | MAX5138BGTE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC V-OUT 16BIT 1CH 16-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 設(shè)置時間： | 5µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，I²C，MICROWIRE?，并行，QSPI?，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-TQFN（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
4
Maxim Integrated
MAX5138/MAX5139
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 2.7V to 5.25V, VDVDD = 2.7V to 5.25V, VAVDD
≥ VDVDD, VAGND = 0V, VREFI = VAVDD - 0.25V, COUT = 200pF, ROUT = 10kΩ,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS (Note 7)
Analog Supply Voltage Range
AVDD
2.7
5.25
V
Digital Supply Voltage Range
DVDD
2.7
VAVDD
V
IAVDD
1
1.6
mA
Supply Current
IDVDD
No load, all digital inputs at 0V or VDVDD
1
10
μA
IAVPD
0.2
2
Power-Down Supply Current
IDVPD
No load, all digital inputs at 0V or VDVDD
0.1
2
μA
TIMING CHARACTERISTICS (Note 8) (Figure 1)
Serial-Clock Frequency
fSCLK
0
30
MHz
SCLK Pulse-Width High
tCH
13
ns
SCLK Pulse-Width Low
tCL
13
ns
CS Fall-to-SCLK Fall Setup Time
tCSS
8
ns
SCLK Fall-to
CS-Rise Hold Time
tCSH
5
ns
DIN-to-SCLK Fall Setup Time
tDS
10
ns
DIN-to-SCLK Fall Hold Time
tDH
2
ns
SCLK Fall to
READY Transition
tSRL
(Note 9)
30
ns
CS Pulse-Width High
tCSW
33
ns
LDAC Pulse Width
tLDACPWL
33
ns
Note 1: Static accuracy tested without load.
Note 2: Linearity is tested within 20mV of AGND and AVDD, allowing for gain and offset error.
Note 3: Codes above 2047 are guaranteed to be within ±9 LSB.
Note 4: Gain and offset tested within 100mV of AGND and AVDD.
Note 5: Guaranteed by design.
Note 6: Device draws current in excess of the specified supply current when a digital input is driven with a voltage of VVI < VDVDD -
0.6V or VVI > 0.5V. At VVI = 2.2V with VDVDD = 5.25V, this current can be as high as 2mA. The SPI inputs are CMOS-input-level
compatible. The 30MHz clock frequency cannot be guaranteed for a minimum signal swing.
Note 7: Excess current from AVDD is 10mA when powered without DVDD. Excess current from DVDD is 1mA when powered without
AVDD.
Note 8: All timing specifications are with respect to the digital input and output thresholds.
Note 9: Maximum daisy-chain clock frequency is limited to 25MHz.
C7
C6
C5
D2
D1
D0
X
COMMAND EXECUTED ON
24th FALLING EDGE OF SCLK
CS
SCLK
DIN
X = DON'T CARE.
tCH
tCL
tCSS
tDH
tCSH
tDS
tSRL
READY
X
tCSW
D3
Figure 1. Serial-Interface Timing Diagram
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