參數(shù)資料
型號: MAX5155ACEE+
廠商: Maxim Integrated Products
文件頁數(shù): 7/16頁
文件大?。?/td> 0K
描述: IC DAC 12BIT DUAL LP SER 16-QSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 100
設置時間: 15µs
位數(shù): 12
數(shù)據(jù)接口: 串行
轉換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 667mW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 16-QSOP
包裝: 管件
輸出數(shù)目和類型: 2 電壓,單極;2 電壓,雙極
采樣率(每秒): *
it trips the comparator. The microprocessor (P) stores
this “high” calibration value. Repeat the process with a
dim light (off) to obtain the dark current calibration.
The P then programs the DAC to set an output voltage
at the midpoint of the two calibrated values.
Applications include tachometers, motion sensing,
automatic readers, and liquid clarity analysis.
Digital Control of Gain and Offset
The two DACs can be used to control the offset and
gain for curve-fitting nonlinear functions, such as trans-
ducer linearization or analog compression/expansion
applications. The input signal is used as the reference
for the gain-adjust DAC, whose output is summed with
the output from the offset-adjust DAC. The relative
weight of each DAC output is adjusted by R1, R2, R3,
and R4 (Figure 14).
Power-Supply Considerations
On power-up, the input and DAC registers clear (set to
zero code). For rated performance, VREF_ should be at
least 1.4V below VDD. Bypass the power supply with a
4.7F capacitor in parallel with a 0.1F capacitor to
AGND. Minimize lead lengths to reduce lead inductance.
Grounding and Layout Considerations
Digital and AC transient signals on AGND can create
noise at the output. Connect AGND to the highest quality
ground available. Use proper grounding techniques,
such as a multilayer board with a low-inductance ground
plane. Carefully lay out the traces between channels to
reduce AC cross-coupling and crosstalk. Wire-wrapped
boards and sockets are not recommended. If noise
becomes an issue, shielding may be required.
MAX5154/MAX5155
Low-Power, Dual, 12-Bit Voltage-Output DACs
with Serial Interface
______________________________________________________________________________________
15
AGND
DGND
MAX5154
MAX5155
DACA
VDD
REFA
VIN
VREF
CS
SCLK
DIN
REFB
R1
R3
R
R4
R2
OUTB
OSB
OUTA
OSA
VOUT
DACB
INPUT
REG A
INPUT
REG B
DAC
REG A
DAC
REG B
– OFFSET
[ ]
VOUT =
=
GAIN
[
]
2NA
4096
NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA.
NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB.
R2
R1+R2
R4
R3
2NB
4096
R4
R3
(VIN
)(
)(1+ ) (VREF
)( )
[
] [
]
SHIFT
REGISTER
Figure 14. Digital Control of Gain and Offset
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