參數(shù)資料
型號: MAX5155BCEE+
廠商: Maxim Integrated Products
文件頁數(shù): 16/16頁
文件大小: 0K
描述: IC DAC 12BIT DUAL LP SER 16-QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 100
設(shè)置時間: 15µs
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 667mW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 管件
輸出數(shù)目和類型: 2 電壓,單極;2 電壓,雙極
采樣率(每秒): *
_______________Detailed Description
The MAX5154/MAX5155 dual, 12-bit, voltage-output
DACs are easily configured with a 3-wire serial inter-
face. These devices include a 16-bit data-in/data-out
shift register, and each DAC has a double-buffered
input composed of an input register and a DAC register
(see
Functional Diagram). In addition, trimmed internal
resistors produce an internal gain of +2V/V that maxi-
mizes output voltage swing. The amplifier’s offset-adjust
pin allows for a DC shift in the DAC’s output.
Both DACs use an inverted R-2R ladder network that pro-
duces a weighted voltage proportional to the input volt-
age value. Each DAC has its own reference input to
facilitate independent full-scale values. Figure 1 depicts a
simplified circuit diagram of one of the two DACs.
Reference Inputs
The reference inputs accept both AC and DC values
with a voltage range extending from 0V to (VDD - 1.4V).
Determine the output voltage using the following equa-
tion (OS_ = AGND):
VOUT = (VREF x NB / 4096) x 2
where NB is the numeric value of the DAC’s binary input
code (0 to 4095) and VREF is the reference voltage.
The reference input impedance ranges from 14k
(1554
hex) to several giga ohms (with an input code of 0000
hex). The reference input capacitance is code dependent
and typically ranges from 15pF with an input code of all
zeros to 50pF with a full-scale input code.
Output Amplifier
The output amplifiers on the MAX5154/MAX5155 have
internal resistors that provide for a gain of +2V/V when
OS_ is connected to AGND. These resistors are
trimmed to minimize gain error. The output amplifiers
have a typical slew rate of 0.75V/s and settle to
1/2LSB within 15s, with a load of 10k
in parallel with
100pF. Loads less than 2k
degrade performance.
The OS_ pin can be used to produce an adjustable off-
set voltage at the output. For instance, to achieve a 1V
offset, apply -1V to the OS_ pin to produce an output
range from 1V to (1V + VREF x 2). Note that the DAC’s
output range is still limited by the maximum output volt-
age specification.
Power-Down Mode
The MAX5154/MAX5155 feature a software-program-
mable shutdown mode that reduces the typical supply
current to 2A. The two DACs can be shutdown inde-
pendently, or simultaneously using the appropriate pro-
gramming command. Enter shutdown mode by writing
the appropriate input-control word (Table 1). In shut-
down mode, the reference inputs
and amplifier out-
puts become high impedance, and the serial
interface remains active. Data in the input registers is
MAX5154/MAX5155
Low-Power, Dual, 12-Bit Voltage-Output DACs
with Serial Interface
_______________________________________________________________________________________
9
Digital Ground
DGND
9
Serial-Data Output
DOUT
10
User-Programmable Output
UPO
11
Power-Down Lockout. The device can-
not be powered down when PDL is low.
PDL
12
Reference for DAC B
REFB
13
Active-Low Clear Input. Resets all reg-
isters to zero. DAC outputs go to 0V.
CL
5
Chip-Select Input
CS
6
Serial-Data Input
DIN
7
Serial Clock Input
SCLK
8
Reference for DAC A
REFA
4
DAC A Offset Adjustment
OSA
3
PIN
DAC A Output Voltage
OUTA
2
Analog Ground
AGND
1
FUNCTION
NAME
14
OSB
DAC B Offset Adjustment
15
OUTB
DAC B Output Voltage
16
VDD
Positive Power Supply
OUT_
OS_
R
SHOWN FOR ALL 1s ON DAC
D0
D9
D10
D11
2R
R
REF_
AGND
Figure 1. Simplified DAC Circuit Diagram
_____________________Pin Description
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