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參數(shù)資料
| 型號： | MAX5189BEEI+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT DUAL 40MHZ 28-QSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 設(shè)置時間： | 25µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-QSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | * |
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
_______________________________________________________________________________________
9
Applications Information
Static and Dynamic
Performance Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best straight-line fit
(closest approximation to the actual transfer curve) or a
line drawn between the endpoints of the transfer func-
tion, once offset and gain errors have been nullified.
The MAX5186/MAX5189 use a straight-line endpoint fit
for INL (and DNL) and the deviations are measured at
every individual step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1LSB. A DNL
error specification no more negative than -1LSB guar-
antees a monotonic transfer function.
Offset Error
The offset error is the difference between the ideal and
the actual offset current/voltage. For the MAX5186/
MAX5189, the offset error is the midpoint value of the
transfer function determined by the endpoints of a
straight-line endpoint fit. This error affects all codes by
the same amount.
Gain Error
Gain error is the difference between the ideal and the
actual output value range. This range represents the
output when all digital inputs are set to 1 minus the out-
put when all digital inputs are set to 0.
Glitch Impulse
A glitch is generated when a DAC switches between
two codes. The largest glitch is usually generated
around the midscale transition, when the input pattern
transitions from 011…111 to 100…000. This occurs due
to timing variations between the bits. The glitch impulse
is found by integrating the voltage of the glitch at the
midscale transition over time. The glitch impulse is usu-
ally specified in pV-s.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the converter’s specified accuracy.
9.6k
*
REFR
REFO
1.2V REF
REN
CURRENT-
SOURCE ARRAY
DAC1 SWITCHES
DAC2 SWITCHES
400
*
OUT1P
OUT1N
OUT2N
400
*
400
* 400*
MSB
DECODE
CLK
OUTPUT
LATCHES
OUTPUT
LATCHES
INPUT
LATCHES
*INTERNAL 400
AND 9.6k
RESISTORS FOR MAX5189 ONLY.
INPUT
LATCHES
AVDD
AGND
CS
DACEN
PD
DVDD
DGND
CREF1
CREF2
MAX5186
MAX5189
MSB
DECODE
D7–D0
Figure 1. Functional Diagram
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