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參數(shù)資料
| 型號(hào)： | MAX5207BEUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT SRL 10UMAX |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 25µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 444.4mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
MAX5204–MAX5207
Low-Cost, Voltage-Output, 16-Bit DACs in MAX
8
_______________________________________________________________________________________
Detailed Description
The MAX5204–MAX5207 serial 16-bit, voltage-output
DACs are easily configured with a 3-wire serial interface.
These devices offer full 16-bit performance with less than
±20LSB integral linearity error and less than ±1LSB dif-
ferential linearity error, thus ensuring monotonic perfor-
mance. Serial data transfer minimizes the number of
package pins required. The MAX5204–MAX5207 include
control-logic circuitry, a 16-bit data-in shift register, and
a DAC register. The MAX5204–MAX5207 output is
buffered and the full-scale output voltage is VREF (typ).
The MAX5204–MAX5207 feature a hardware reset input
(CLR) that when pulled low clears the DAC output to
zero code 0000 hex (MAX5205/MAX5207) or resets the
DAC output to midscale code 8000 hex (MAX5204/
MAX5206). For normal operation, connect CLR to VDD.
Reference Input
The MAX5204/MAX5205 (+5V supply) use an external
reference between 4V to VDD, while the MAX5206/
MAX5207 (+3V supply) use an external reference from
2V to VDD. The DAC output range is from 0 to VREF.
Digital Interface
The MAX5204–MAX5207 digital interface is a standard
3-wire connection compatible with SPI/QSPI/
MICROWIRE and most DSP interfaces. All of the digital
input pins (CS, SCLK, DIN, CLR, and LDAC) are TTL
compatible. SCLK can accept clock frequencies as
high as 10MHz for a +5V supply and 10MHz for a +3V
or +3.3V supply.
One of two methods can be used when interfacing and
updating the MAX5204–MAX5207. The first requires
Pin Description
PIN
NAME
FUNCTION
1
CLR
Reset DAC Active-Low Input. Pull CLR low to reset the DAC output to midscale output (8000 hex) for
MAX5204/MAX5206 and to zero-scale output (0000 hex) for MAX5205/MAX5207. For normal operation,
connect CLR to VDD.
2
REF
External Reference Voltage Input
3
AGND
Analog Ground
4VDD
Positive Supply Voltage. Bypass VDD to AGND with a 10F capacitor in parallel with a 0.1F capacitor.
5
OUT
DAC Output Voltage
6
CS
Active-Low Chip-Select Input
7
LDAC
Load DAC Input
8
DIN
Serial Data Input
9
SCLK
Serial Clock Input. Duty cycle must be 40% to 60%.
10
DGND
Digital Ground
CLR
AGND
REF
16-BIT DAC
16-BIT DATA LATCH
DIN
SCLK
CS
CONTROL
LOGIC
LDAC
OUT
DGND
VDD
MAX5204–
MAX5207
SERIAL INPUT REGISTER
BUFFER
Figure 1. MAX5204–MAX5207 Simplified Functional Diagram
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