參數(shù)資料
型號(hào): MAX522CSA
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: Triple Low-Power Drivers And Receivers 16-SOIC -40 to 85
中文描述: DUAL, SERIAL INPUT LOADING, 70 us SETTLING TIME, 8-BIT DAC, PDSO8
封裝: 0.150 INCH, ROHS COMPLIANT, SOP-8
文件頁(yè)數(shù): 3/12頁(yè)
文件大?。?/td> 116K
代理商: MAX522CSA
M
Dual, 8-Bit, Voltage-Output
S erial DAC in 8-Pin S O Pac kage
_______________________________________________________________________________________
3
Note 2:
Reduced digital code range (code 24 through code 232) is due to swing limitations of the output amplifiers. See Typical
Operating Characteristics.
Note 3:
Reference input resistance is code dependent. The lowest input resistance occurs at code 55hex. Refer to the Reference
Inputsection in the Detailed Description
Note 4:
Guaranteed by design. Not production tested.
Note 5:
Input capacitance is code dependent. The highest capacitance occurs at code 00hex.
CONDITIONS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +5.5V, REF = V
DD
, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
Voltage-Output Slew Rate
SR
C
L
= 0.1μF (DAC A), C
L
= 0.01μF (DAC B)
0.1
70
70
V/μs
Voltage-Output Settling Time
To ±
1
2
LSB
μs
Digital Feedthrough
and Crosstalk
All 0s to all 1s
10
nV-s
Supply Voltage Range
V
DD
2.7
5.5
2.8
2.5
V
Shutdown Supply Current
V
DD
= 5.5V
0.1
μA
C
L
= 0.1μF (DAC A)
C
L
= 0.01μF (DAC B)
Supply Current
I
DD
All inputs = 0V
1.3
0.9
mA
DYNAMIC PERFORMANCE
POWER SUPPLIES
V
DD
= 5.5V
V
DD
= 3.6V
TIMING CHARACTERISTICS
(Note 4)
(V
DD
= +2.7V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
CONDITIONS
ns
200
t
CSPWH
–—Pulse Width High
ns
100
t
CL
SCLK Pulse Width Low
ns
100
t
CH
SCLK Pulse Width High
ns
50
t
DH
DIN to SCLK Rise Hold Time
ns
50
t
DS
DIN to SCLK Rise Setup Time
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ns
ns
150
150
t
CSS
t
CSH
–—Fall to SCLK Rise Setup Time
SCLK Rise to –—Rise Setup Time
SERIAL INTERFACE TIMING
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