參數(shù)資料
型號(hào)： MAX522ESA+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 6/12頁(yè)
文件大?。?/td> 0K
描述： IC DAC 8BIT DUAL SERIAL 8-SOIC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
設(shè)置時(shí)間： 70µs
位數(shù)： 8
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電壓，單極
采樣率（每秒）： *
MAX522
Dual, 8-Bit, Voltage-Output
Serial DAC in 8-Pin SO Package
_______________________________________________________________________________________
3
Note 2: Reduced digital code range (code 24 through code 232) is due to swing limitations of the output amplifiers. See
Typical
Operating Characteristics.
Note 3: Reference input resistance is code dependent. The lowest input resistance occurs at code 55hex. Refer to the
Reference
Input section in the Detailed Description.
Note 4: Guaranteed by design. Not production tested.
Note 5: Input capacitance is code dependent. The highest capacitance occurs at code 00hex.
CONDITIONS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V, REF = VDD, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Voltage-Output Slew Rate
SR
CL = 0.1F (DAC A), CL = 0.01F (DAC B)
0.1
V/s
70
Voltage-Output Settling Time
To ±12LSB
s
Digital Feedthrough
and Crosstalk
All 0s to all 1s
10
nV-s
Supply Voltage Range
VDD
2.7
5.5
V
Shutdown Supply Current
VDD = 5.5V
0.1
A
CL = 0.1F (DAC A)
CL = 0.01F (DAC B)
70
Supply Current
IDD
All inputs = 0V
1.3
2.8
mA
0.9
2.5
DYNAMIC PERFORMANCE
POWER SUPPLIES
VDD = 5.5V
VDD = 3.6V
TIMING CHARACTERISTICS (Note 4)
(VDD = +2.7V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.)
CONDITIONS
ns
200
tCSPWH
–
C
—
S
–
Pulse Width High
ns
100
tCL
SCLK Pulse Width Low
ns
100
tCH
SCLK Pulse Width High
ns
50
tDH
DIN to SCLK Rise Hold Time
ns
50
tDS
DIN to SCLK Rise Setup Time
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ns
150
tCSS
–
C
—
S
–
Fall to SCLK Rise Setup Time
ns
150
tCSH
SCLK Rise to
–
C
—
S
–
Rise Setup Time
SERIAL INTERFACE TIMING
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