參數資料
型號: MAX5253BEAP+T
廠商: Maxim Integrated Products
文件頁數: 11/16頁
文件大小: 0K
描述: IC DAC 12BIT QUAD 3V 20-SSOP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,000
設置時間: 16µs
位數: 12
數據接口: 串行
轉換器數目: 4
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 20-SSOP
包裝: 帶卷 (TR)
輸出數目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): *
0
-4
-8
-12
-16
-20
100
560k
1.12M
1.68M
2.24M
2.8M
MAX5253-06
RELATIVE
OUTPUT
(dB)
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
FREQUENCY (Hz)
REFAB SWEPT 0.67VP-P
RL = 5k
CL = 100pF
INL
(LSB)
-5
0
0.5
1.0
1.5
2.0
REFERENCE VOLTAGE (V)
MAX5253-01
2.5
1
0
-1
-2
-3
-4
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE
RL = 5k
1000
950
900
850
800
750
700
650
600
550
500
-55 -40 -20
0
20 40
60
80
125
100
MAX5253-04
SUPPLY
CURRENT
(
A)
SUPPLY CURRENT
vs. TEMPERATURE
TEMPERATURE (
°C)
CODE = FFF HEX
__________________________________________Typical Operating Characteristics
(VDD = +3.3V, TA = +25°C, unless otherwise noted.)
MAX5253
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
4
_______________________________________________________________________________________
TIMING CHARACTERISTICS
(VDD = +3.0V to +3.6V, AGND = DGND = 0V, REFAB = REFCD =1.25V, RL = 5k
, CL = 100pF, TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25°C. Output buffer connected in unity-gain configuration (Figure 9).)
CONDITIONS
tD02
SCLK Fall to DOUT Valid
Propagation Delay
tD01
SCLK Rise to DOUT Valid
Propagation Delay
ns
100
tCP
SCLK Clock Period
ns
0
tDH
DIN Hold Time
ns
40
tDS
DIN Setup Time
ns
0
tCSH
SCLK Rise to CS Rise Hold Time
ns
40
tCSS
CS Fall to SCLK Rise Setup Time
ns
40
tCH
SCLK Pulse Width High
ns
40
tCL
SCLK Pulse Width Low
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ns
100
tCSW
CS Pulse Width High
ns
40
tCS1
CS Rise to SCLK Rise Hold Time
ns
40
tCS0
SCLK Rise to CS Fall Delay
CL = 200pF
120
ns
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