參數(shù)資料
型號(hào)： MAX5259EEE+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 17/20頁(yè)
文件大小： 0K
描述： IC DAC 8BIT OCTAL 3V 16-QSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
設(shè)置時(shí)間： 10µs
位數(shù)： 8
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 8
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-QSOP
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 8 電壓，單極
采樣率（每秒）： *
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
6
_______________________________________________________________________________________
TIMING CHARACTERISTICS (MAX5259)
(VREF = +2.5V, GND = 0, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and
TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDD Rise-to-CS Fall-Setup Time
tVDCS
5
s
LDAC Pulse Width Low
tLDAC
40
20
ns
CS Rise-to-LDAC Fall-Setup Time
(Note 4)
tCLL
40
ns
CS Pulse Width High
tCSW
90
ns
SCLK Clock Frequency (Note 5)
fCLK
10
MHz
SCLK Pulse Width High
tCH
40
ns
SCLK Pulse Width Low
tCL
40
ns
CS Fall-to-SCLK Rise-Setup Time
tCSS
40
ns
SCLK Rise-to-
CS Rise-Hold Time
tCSH
0ns
DIN to SCLK Rise-to-Setup Time
tDS
40
ns
DIN to SCLK Rise-to-Hold Time
tDH
0ns
SCLK Rise-to-DOUT Valid
Propagation Delay (Note 6)
tDO1
200
ns
SCLK Fall-to-DOUT Valid
Propagation Delay (Note 7)
tDO2
210
ns
CS Rise-to-SCLK Rise-Setup
Time
tCS1
40
ns
Note 1: INL and DNL are measured with RL referenced to ground. Nonlinearity is measured from the first code that is greater than or
equal to the maximum offset specification to code FF hex (full scale). (See DAC Linearity and Voltage Offset section.)
Note 2: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of the final value of VOUT.
Note 3: Guaranteed by design, not production tested.
Note 4: If LDAC is activated prior to the rising edge of CS, it must remain low for tLDAC or longer after CS goes high.
Note 5: When DOUT is not used. If DOUT is used, fCLK (max) is 4MHz due to SCLK to DOUT propagation delay.
Note 6: Serial data is clocked-out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of VDD).
Note 7: Serial data is clocked-out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of VDD).
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參數(shù)描述
MAX525AC 制造商:Maxim Integrated Products 功能描述:
MAX525ACAP 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
MAX525ACAP+ 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit 4Ch Precision DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
MAX525ACAP+T 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit 4Ch Precision DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
MAX525ACAP-T 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
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