參數(shù)資料
型號(hào): MAX525ACAP+
廠商: Maxim Integrated Products
文件頁數(shù): 2/16頁
文件大?。?/td> 0K
描述: IC DAC 12BIT QUAD LP 20-SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 66
設(shè)置時(shí)間: 12µs
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 20-SSOP
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): *
產(chǎn)品目錄頁面: 1394 (CN2011-ZH PDF)
C1
C0
MAX525
Figure 5 shows the serial-interface timing requirements.
The chip-select pin (CS) must be low to enable the
DAC’s serial interface. When CS is high, the interface
control circuitry is disabled. CS must go low at least
tCSS before the rising serial clock (SCLK) edge to prop-
erly clock in the first bit. When CS is low, data is
clocked into the internal shift register through the serial-
data input pin (DIN) on SCLK’s rising edge. The maxi-
mum guaranteed clock frequency is 10MHz. Data is
latched into the appropriate MAX525 input/DAC regis-
ters on CS’s rising edge.
The programming command Load-All-DACs-From-Shift-
Register allows all input and DAC registers to be simul-
taneously loaded with the same digital code from the
input shift register. The no operation (NOP) command
leaves the register contents unaffected and is useful
when the MAX525 is configured in a daisy chain (see
the Daisy Chaining Devices section). The command to
change the clock edge on which serial data is shifted
out of DOUT also loads data from all input registers to
their respective DAC registers.
Serial-Data Output (DOUT)
The serial-data output, DOUT, is the internal shift regis-
ter’s output. The MAX525 can be programmed so that
data is clocked out of DOUT on SCLK’s rising edge
(Mode 1) or falling edge (Mode 0). In Mode 0, output
data at DOUT lags input data at DIN by 16.5 clock
cycles, maintaining compatibility with MICROWIRE,
SPI/QSPI, and other serial interfaces. In Mode 1, output
data lags input data by 16 clock cycles. On power-up,
DOUT defaults to Mode 0 timing.
User-Programmable Logic Output (UPO)
The user-programmable logic output, UPO, allows an
external device to be controlled through the MAX525
serial interface (Table 1).
Low-Power, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
10
______________________________________________________________________________________
Table 1. Serial-Interface Programming Commands
00
No operation (NOP) to DAC registers
00
11
UPO goes low (default)
Shutdown (provided PDL = 1)
10
Load all DAC registers from shift register (start-up).
Load input register A; DAC registers unchanged.
Load input register B; DAC registers unchanged.
Load input register C; DAC registers unchanged.
Load input register D; DAC registers unchanged.
Load input register A; all DAC registers updated.
Load input register B; all DAC registers updated.
Load input register C; all DAC registers updated.
Load input register D; all DAC registers updated.
01
00
01
10
11
00
01
10
11
Update all DAC registers from their respective input registers (start-up).
UPO goes high
00
10
00
10
01
11
XXXXXXXXXXXX
16-BIT SERIAL WORD
XXXXXXXXXXXX
12-bit DAC data
XXXXXXXXXXXX
12-bit DAC data
10
XXXXXXXXXXXX
Mode 0, DOUT clocked out on SCLK’s falling edge. All DAC registers
updated (default).
XXXXXXXXXXXX
11
Mode 1, DOUT clocked out on SCLK’s rising edge. All DAC registers
updated.
10
“X” = Don’t care
A1
A0
C1
C0
D11.................D0
MSB
LSB
FUNCTION
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