參數(shù)資料
型號: MAX5355EUA+T
廠商: Maxim Integrated Products
文件頁數(shù): 12/16頁
文件大小: 0K
描述: IC DAC 10BIT 3.3V VOLT OUT 8UMAX
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
設置時間: 10µs
位數(shù): 10
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 330mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 8-uMAX
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): *
MAX5354/MAX5355
10-Bit Voltage-Output DACs
in 8-Pin MAX
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS: MAX5355 (continued)
(VDD = +3.15V to +3.6V, REF = 1.25V, GND = 0V, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25°C. Output buffer connected in unity-gain configuration (Figure 8).)
ns
CONDITIONS
40
tCH
SCLK Pulse Width High
ns
100
tCP
SCLK Clock Period
ns
40
tCSS
CS Fall to SCLK Rise Setup Time
ns
40
tDS
DIN Setup Time
ns
0
tCSH
SCLK Rise to CS Rise Hold Time
ns
40
tCL
SCLK Pulse Width Low
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ns
40
tCS1
CS Rise to SCLK Rise Hold Time
ns
0
tDH
DIN Hold Time
ns
100
tCSW
CS Pulse Width High
ns
40
tCS0
SCLK Rise to CS Fall Delay
Note 4: Guaranteed from code 6 to code 1023 in unity-gain configuration.
Note 5: Accuracy is better than 1LSB for VOUT = 8mV to VDD - 150mV, guaranteed by a power-supply rejection test at the
end points.
Note 6: RL = ∞, digital inputs at GND or VDD.
TIMING CHARACTERISTICS (Figure 6)
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