參數(shù)資料
型號(hào): MAX536BCWE+
廠商: Maxim Integrated Products
文件頁數(shù): 5/24頁
文件大小: 0K
描述: IC DAC QUAD CALBRTD 12BIT 16SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 46
設(shè)置時(shí)間: 3µs
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 雙 ±
功率耗散(最大): 762mW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): *
產(chǎn)品目錄頁面: 1394 (CN2011-ZH PDF)
MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
The input impedance at each reference input is code
dependent, ranging from a low value of typically 6k
(with an input code of 0101 0101 0101) to a high value
of 60k
(with an input code of 0000 0000 0000). Since
the input impedance at the reference pins is code
dependent, load regulation of the reference source is
important.
The REFAB and REFCD reference inputs have a 5k
guaranteed minimum input impedance. When the two
reference inputs are driven from the same source, the
effective minimum impedance becomes 2.5k
.
The reference input capacitance is also code depen-
dent and typically ranges from 125pF to 300pF.
Output Buffer Amplifiers
All MAX536/MAX537 voltage outputs are internally
buffered by precision unity-gain followers with a typical
slew rate of 5V/
s for the MAX536 and 3V/s for the
MAX537.
With a full-scale transition at the MAX536 output (0 to
8V or 8V to 0), the typical settling time to ±0.5 LSB is
3
s when loaded with 5k in parallel with 100pF (loads
less than 5k
degrade performance).
With a full-scale transition at the MAX537 output (0 to
2.5V or 2.5V to 0), the typical settling time to ±0.5 LSB
is 5
s when loaded with 5k in parallel with 100pF
(loads less than 5k
degrade performance).
Output dynamic responses and settling performances
of the MAX536/MAX537 output amplifier are shown in
the Typical Operating Characteristics.
Serial-Interface Configurations
The MAX536/MAX537’s 3-wire or 4-wire serial interface is
compatible with both MICROWIRE (Figure 2) and
SPI/QSPI (Figure 3). In Figures 2 and 3, LDAC can be tied
either high or low for a 3-wire interface, or used as the
fourth input with a 4-wire interface. The connection
between SDO and the serial-interface port is not neces-
sary, but may be used for data echo. (Data held in the
shift register of the MAX536/MAX537 can be shifted out
of SDO and returned to the microprocessor for data veri-
fication; data in the MAX536/MAX537 input/DAC regis-
ters cannot be read.)
With a 3-wire interface (CS, SCK, SDI) and LDAC tied
high, the DACs are double-buffered. In this mode,
depending on the command issued through the serial
interface, the input register(s) may be loaded
without affecting the DAC register(s), the DAC register(s)
can be loaded directly, or all four DAC registers may be
simultaneously updated from the input registers. With a 3-
wire interface (CS, SCK, SDI) and LDAC tied low (Figure
SCK
SDI
SDO*
CS
LDAC**
SK
SO
SI*
I/O
MAX536
MAX537
MICROWIRE
PORT
5V
*THE SDO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536,
BUT MAY BE USED FOR READBACK PURPOSES.
**THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE.
THE MAX537 HAS AN INTERNAL ACTIVE PULLUP TO VDD,
SO RP IS NOT NECESSARY.
RP
1k
Figure 2. Connections for MICROWIRE
Figure 3. Connections for SPI/QSPI
SDO*
SDI
SCK
CS
LDAC**
MISO*
MOSI
SCK
I/O
SPI/QSPI
PORT
SS
5V
CPOL = 0, CPHA = 0
*THE SDO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536,
BUT MAY BE USED FOR READBACK PURPOSES.
**THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE.
MAX536
MAX537
RP
1k
THE MAX537 HAS AN INTERNAL ACTIVE PULLUP TO VDD,
SO RP IS NOT NECESSARY.
_______________________________________________________________________________________
13
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