參數資料
型號: MAX5380NEUK+T
廠商: Maxim Integrated Products
文件頁數: 7/12頁
文件大?。?/td> 0K
描述: IC DAC 8BIT 2WIRE SER SOT23-5
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
設置時間: 20µs
位數: 8
數據接口: 串行
轉換器數目: 1
電壓電源: 單電源
功率耗散(最大): 571mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SC-74A,SOT-753
供應商設備封裝: SOT-23-5
包裝: 帶卷 (TR)
輸出數目和類型: 1 電壓,單極
采樣率(每秒): *
MAX5380/MAX5381/MAX5382
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
4
_______________________________________________________________________________________
TIMING CHARACTERISTICS (continued)
(Figure 3; VDD = +2.7V to +3.6V (MAX5380), VDD = +4.5V to +5.5V (MAX5381), VDD = +2.7V to +5.5V (MAX5382); RL = 10k
;
CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.) (Note 7)
Note 1: Guaranteed from code 5 to code 255.
Note 2: The offset value extrapolated from the range over which the INL is guaranteed.
Note 3: MAX5382 tested at VDD = +5V ±10%.
Note 4: MAX5380 tested at VDD = +3V ±10%, MAX5381 tested at VDD = 5V ±10%.
Note 5: Actual output voltages at full scale are 255/256 x VREF.
Note 6: Output settling time is measured by taking the code from code 5 to 255, and from code 255 to 5.
Note 7: Guaranteed by design.
Rise Time of Both SDA and
SCL Signals
tr
300
ns
Fall Time of Both SDA and
SCL Signals
tf
CONDITIONS
300
ns
Setup Time for STOP Condition
tSU:STO
0.6
s
Capacitive Load for Each
Bus Line
Cb
400
pF
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Typical Operating Characteristics
(VDD = +3.0V (MAX5380), VDD = +5.0V (MAX5381/MAX5382); RL = 10k
, TA = +25°C, unless otherwise noted.)
-0.050
-0.075
-0.100
-0.025
0
0.025
0.050
0.075
0
100
200
50
150
250
300
INTEGRAL NONLINEARITY vs. CODE
MAX5380/1/2-01
CODE
INL
(LSB)
0
-0.10
-0.15
-0.05
-0.20
2.5
4.0
3.0
3.5
4.5
5.0
5.5
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX5380/1/2-02
SUPPLY VOLTAGE (V)
INL
(LSB)
0
-0.10
-0.15
-0.05
-0.20
-40
20
-20
0
40
60
80
100
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX5380/1/2-03
TEMPERATURE (°C)
INL
(LSB)
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