參數(shù)資料
型號(hào): MAX5392LAUE+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 11/16頁(yè)
文件大?。?/td> 0K
描述: IC DGTL POT 256POS 10K 16TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
接片: 256
電阻(歐姆): 10k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 35 ppm/°C
存儲(chǔ)器類型: 易失
接口: I²C(設(shè)備位址)
電源電壓: 1.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
MAX5392
4 ______________________________________________________________________________________
Figure 1. Voltage-Divider and Variable Resistor Configurations
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.7V to +5.5V, VH_ = VDD, VL_ = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +1.8V,
TA = +25NC.) (Note 1)
Note 1: All devices are 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design
and characterization.
Note 2: DNL and INL are measured with the potentiometer configured as a voltage-divider (Figure 1) with H_ = VDD and L_ = GND.
The wiper terminal is unloaded and measured with a high-input-impedance voltmeter.
Note 3: R-DNL and R-INL are measured with the potentiometer configured as a variable resistor (Figure 1). DNL and INL are mea-
sured with the potentiometer configured as a variable resistor. H_ is unconnected and L_ = GND. For VDD = +5V, the wiper
terminal is driven with a source current of 400FA for the 10kI configuration, 80FA for the 50kI configuration, and 40FA for
the 100kI configuration. For VDD = +1.7V, the wiper terminal is driven with a source current of 150FA for the 10kI configu-
ration, 30FA for the 50kI configuration, and 15FA for the 100kI configuration.
Note 4: The wiper resistance is the worst value measured by injecting the currents given in Note 3 to W_ with L_ = GND.
RW_ = (VW_ - VH_)/IW_.
Note 5: Drive HA with a 1kHz GND to VDD amplitude tone. LA = LB = GND. No load. WB is at midscale with a 10pF load. Measure
WB.
Note 6: The wiper-settling time is the worst-case 0 to 50% rise time, measured between tap 0 and tap 127. H_ = VDD, L_ = GND,
and the wiper terminal is loaded with 10pF capacitance to ground.
Note 7: Digital timing is guaranteed by design and characterization, not production tested.
Note 8: The SCL clock period includes rise and fall times (tR = tF). All digital input signals are specified with tR = tF = 2ns and timed
from a voltage level of (VIL + VIH)/2.
Note 9: An appropriate bus pullup resistance must be selected depending on board capacitance. For I2C-bus specification infor-
mation from NXP Semiconductor (formerly Philips Semiconductor), refer to the UM10204: I2C-Bus Specification and User
Manual.
H
L
W
N.C.
L
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Data Setup Time
tSU:DAT
100
ns
Data Hold Time
tHD:DAT
0
F
s
SDA, SCL Rise Time
tR
0.3
F
s
SDA, SCL Fall
tF
0.3
F
s
Setup Time for STOP Condition
tSU:STO
0.6
F
s
Bus Free Time Between STOP and
START Condition
tBUF
Minimum power-up rate = 0.2V/Fs
1.3
F
s
Pulse Suppressed Spike Width
tSP
50
ns
Capacitive Load for Each Bus
CB
(Note 9)
400
pF
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