參數(shù)資料
型號: MAX5393NAUD+
廠商: Maxim Integrated Products
文件頁數(shù): 2/14頁
文件大小: 0K
描述: IC POT DGTL DUAL 256TAP 14TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 96
接片: 256
電阻(歐姆): 100k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 35 ppm/°C
存儲器類型: 易失
接口: 3 線串行(芯片選擇)
電源電壓: 1.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 管件
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
MAX5391/MAX5393
10 _____________________________________________________________________________________
REG A: The data byte writes to register A, and the wiper
of potentiometer A moves to the appropriate position at
the rising edge of CS. D[7:0] indicates the position of the
wiper. D[7:0] = 00h moves the wiper to the position clos-
est to LA. D[7:0] = FFh moves the wiper closest to HA.
D[7:0] is 80h following power-on.
REG B: The data byte writes to register B, and the wiper
of potentiometer B moves to the appropriate position at
the rising edge of CS. D[7:0] indicates the position of the
wiper. D[7:0] = 00h moves the wiper to the position clos-
est to LB. D[7:0] = FFh moves the wiper to the position
closest to HB. D[7:0] is 80h following power-on.
REG A and B: The data byte writes to registers A and
B, and the wipers of potentiometers A and B move to the
appropriate position. D[7:0] indicates the position of the
wiper. D[7:0] = 00h moves the wiper to the position clos-
est to L_. D[7:0] = FFh moves the wiper to the position
closest to H_. D[7:0] is 80h following power-on.
Applications Information
Variable Gain Amplifier
Figure 4 shows a potentiometer adjusting the gain of a
noninverting amplifier. Figure 5 shows a potentiometer
adjusting the gain of an inverting amplifier.
Adjustable Dual Regulator
Figure 6 shows an adjustable dual linear regulator using
a dual potentiometer as two variable resistors.
Adjustable Voltage Reference
Figure 7 shows an adjustable voltage reference circuit
using a potentiometer as a voltage divider.
Figure 3. SPI Timing Diagram
SCLK
CS
DIN
tCSO
tCSS
tCL
tDS
tDH
tCH
tCSW
tCS1
tCSH
tCP
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