參數(shù)資料
型號(hào): MAX5405EUB+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 4/10頁(yè)
文件大小: 0K
描述: IC DGTL POT DUAL 256-TAP 10-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
接片: 256
電阻(歐姆): 100k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 35 ppm/°C
存儲(chǔ)器類型: 易失
接口: 3 線串行(芯片選擇)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1399 (CN2011-ZH PDF)
MAX5403/MAX5404/MAX5405
Dual 256-Tap, Low-Drift,
Digital Potentiometers in 10-MAX
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V, unless otherwise noted. VH = VDD, VL = 0, TA = TMIN to TMAX. Typical values are at VDD = +5V, TA = +25°C,
unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX5403
7.5
10
12.5
MAX5404
37.5
50
62.5
End-to-End Resistance
RHL
MAX5405
75
100
125
k
DIGITAL INPUTS
Input High Voltage
VIH
0.7 VDD
V
Input Low Voltage
VIL
0.3 VDD
V
Input Leakage Current
±1.0
A
Input Capacitance
5pF
TIMING CHARACTERISTICS (ANALOG)
MAX5403
100
MAX5404
325
Wiper-Settling Time
tS
MAX5405
650
ns
TIMING CHARACTERISTICS (DIGITAL) (Note 5)
Maximum SCLK Frequency
10
MHz
SCLK Clock Period
tCP
100
ns
SCLK Pulse Width High
tCH
40
ns
SCLK Pulse Width Low
tCL
40
ns
CS Fall to SCLK Rise Setup Time
tCSS
40
ns
SCLK Rise to
CS Rise Hold Time
tCSH
0ns
DIN Setup Time
tDS
40
ns
DIN Hold Time
tDH
0ns
SCLK Rise to
CS Fall Delay
tCS0
10
ns
CS Rise to SCLK Rise Hold
tCS1
40
ns
CS Pulse Width High
tCSW
100
ns
POWER SUPPLIES
Supply Voltage
VDD
2.7
5.5
V
VDD = +5V
0.8
5
A
Supply Current
IDD
CS = SCLK = DIN = VDD
VDD = +2.7V
0.1
A
Note 1: Linearity is defined in terms of the HX to LX code-dependent resistance.
Note 2: The DNL and INL are measured with the potentiometer configured as a voltage divider with HX = VDD and LX = 0. The wiper
terminal is unloaded and measured with an ideal voltmeter.
Note 3: The DNL and INL are measured with the potentiometer configured as a variable resistor. For the 3-terminal potentiometer
(Pot A), HA is unconnected and LA = 0. For the 2-terminal potentiometer (Pot B), only LB = 0. At VDD = +5V, the wiper termi-
nal is driven with a source current of 400A for the 10k
configuration, 80A for the 50k configuration, and 40A for the
100k
configuration. At VDD = +3V, 200A/40A/20A for 10k/50k/100k configuration respectively.
Note 4: The wiper resistance is the worst value measured by injecting into WX, a current IW = VDD / RHL.
Note 5: Digital timing is guaranteed by design.
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