參數(shù)資料
型號: MAX5410EEE+
廠商: Maxim Integrated Products
文件頁數(shù): 12/13頁
文件大?。?/td> 0K
描述: IC DGTL POT DUAL AUDIO 16-QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 100
接片: 32
電阻(歐姆): 10k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 35 ppm/°C
存儲器類型: 易失
接口: 4 線 SPI(芯片選擇)
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 管件
產(chǎn)品目錄頁面: 1399 (CN2011-ZH PDF)
MAX5408–MAX5411
The digital output, DOUT, lags the digital input signal,
DIN by 8.5 clock cycles. Force
CS high to disable
DOUT, placing DOUT in three-state mode. Force
CS
low to enable DOUT and disable three-state mode.
Force
CS high, after a word has been written to the
MAX5408–MAX5411 to make a readback request. The
next
CS low period writes the requested data to DOUT.
A readback request overwrites any previous data in the
shift register. Note that the data appears at DOUT in
the order: A0, A1, A2, D4, D3, D2, D1, D0. A0 will be
available after the first high-to-low transition of SCLK
when
CS is low. The input continues to load the shift
register while data is being read out of the MAX5408–
MAX5411. The input data appears at DOUT 8.5 clock
cycles later. A
CS transition from low-to-high latches
the input data. For any control byte, the state of SCLK
must be the same for both
CS low-to-high transitions
and
CS high-to-low transitions in order to preserve the
data at DOUT while
CS transitions. For proper opera-
tion, ensure that the input data remains valid on both
the SCLK rising and falling edges when daisy chaining
multiple devices.
Zero-Crossing Detection
The zero-crossing detection register enables the zero-
crossing detect feature. The zero-crossing detect fea-
ture reduces the audible noise (“clicks and pops”) that
result from wiper transitions. The wiper changes posi-
tion only when the voltage at L_ is the same as the volt-
age at H_. Each wiper has a zero-crossing and timeout
Dual, Audio, Log Taper Digital Potentiometers
8
_______________________________________________________________________________________
DATA BIT
VALUE
FUNCTION
0
Disable wiper W0A zero-crossing detection circuit
D4
1
Enable wiper W0A zero-crossing detection circuit
D3
“don’t care”
No change
0
Disable wiper W1A zero-crossing detection circuit
D2
1
Enable wiper W1A zero-crossing detection circuit
D1
“don’t care”
No change
D0
“don’t care”
No change
Table 5. Zero-Crossing Detection Register Bit Definitions for MAX5408/MAX5410
DATA BIT
VALUE
FUNCTION
0
Disable wiper W0A zero-crossing detection circuit
D4
1
Enable wiper W0A zero-crossing detection circuit
0
Disable wiper W0B zero-crossing detection circuit
D3
1
Enable wiper W0B zero-crossing detection circuit
0
Disable wiper W1A zero-crossing detection circuit
D2
1
Enable wiper W1A zero-crossing detection circuit
0
Disable wiper W1B zero-crossing detection circuit
D1
1
Enable wiper W1B zero-crossing detection circuit
D0
“don’t care”
No change
Table 6. Zero-Crossing Detection Register Bit Definitions for MAX5409/MAX5411
POSITION
OUTPUT LEVEL (dB)
00
1-2
2-4
3-6
4-8
..
.
..
.
30
-60
31
-62
MUTE
<-90
Table 7. Attenuation and Wiper Position
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