參數(shù)資料
型號(hào): MAX5421CEUB+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 2/9頁(yè)
文件大小: 0K
描述: IC VOLTAGE DIVIDER DGLT 10MSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
接片: 4
電阻(歐姆): 15k
電路數(shù): 1
存儲(chǔ)器類(lèi)型: 易失
接口: 2 輸入并口
電源電壓: 4.75 V ~ 5.25 V,±0.0 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 管件
MAX5420/MAX5421
Digitally Programmable Precision
Voltage Divider for PGAs
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +5V ±5%, VSS = -5V ±5% or VSS = GND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND ..............................................................-0.3V to +6V
VSS to GND...............................................................+0.3V to -6V
D0, D1 to GND ...........................................-0.3V to (VDD + 0.3V)
H, L, W, MATCH_ to GND ................(VSS - 0.3V) to (VDD + 0.3V)
Input and Output Latchup Immunity.................................±50mA
Continuous Power Dissipation (TA = +70°C)
8-Pin MAX (derate 4.1mW/°C above +70°C) .............333mW
10-Pin MAX (derate 5.6mW/°C above +70°C) ...........444mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX542_A
±0.025
MAX542_B
±0.09
Divider Ratio Accuracy
MAX542_C
±0.5
%
H-to-L Resistance
RHL
(Figure 1)
15
k
Input Resistance at H
RH
15
k
VSS = -5V
300
Ratio = 1
VSS = 0
500
Input Resistance at W
RW
Ratio = 2, 4, 8
8
k
Capacitance at H, L, W,
MATCH_H, MATCH_L
CANALOG
5pF
VSS = -5V
300
Ratio = 1
VSS = 0
500
Matching Resistor
MAX5421
Ratio = 2, 4, 8
8
k
DYNAMIC PERFORMANCE
Switching Time
tS
VDD = +5V, VSS = -5V, digital input 0 to +3V,
VW settles to 0.02% of final value with 2pF
capacitive load. Circuit of Figure 2.
0.5
s
DIGITAL INPUTS
Input High Voltage
VIH
2.4
Input Low Voltage
VIL
0.8
V
Input Leakage Current
D1, D0 = VDD or GND
±1
A
Input Capacitance
5pF
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