Dual, 256-Tap, Nonvolatile, I2C-Interface, Digital Poten" />
參數(shù)資料
型號： MAX5477ETE+T
廠商： Maxim Integrated Products
文件頁數(shù)： 3/16頁
文件大?。?/td> 0K
描述： IC DGTL POT DUAL 256TAP 16-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
接片： 256
電阻（歐姆）： 10k
電路數(shù)： 2
溫度系數(shù)： 標(biāo)準(zhǔn)值 70 ppm/°C
存儲器類型： 非易失
接口： I²C（設(shè)備位址）
電源電壓： 2.7 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 16-TQFN（3x3）
包裝： 帶卷 (TR)
MAX5477/MAX5478/MAX5479
Dual, 256-Tap, Nonvolatile, I2C-Interface,
Digital Potentiometers
______________________________________________________________________________________
11
Digital Interface
The MAX5477/MAX5478/MAX5479 feature an internal,
nonvolatile EEPROM that stores the wiper state for ini-
tialization during power-up. The shift register decodes
the command and address bytes, routing the data to
the proper memory registers. Data written to a volatile
memory register immediately updates the wiper posi-
tion, or writes data to a nonvolatile register for storage
(see Table 3).
The volatile register retains data as long as the device
is powered. Removing power clears the volatile regis-
ter. The nonvolatile register retains data even after
power is removed. Upon power-up, the power-on reset
circuitry controls the transfer of data from the non-
volatile register to the volatile register.
Write Protect (WP)
A write-protect feature prevents accidental overwriting of
the EEPROM. Connect WP to VDD or leave unconnected
to prevent any EEPROM write cycles. Writing to the
volatile register (VREG) while WP = 1 updates the wiper
position with the protected data stored in the nonvolatile
register (NVREG). Connect WP to GND to allow write
commands to the EEPROM and to update the wiper
position from either the value in the EEPROM or directly
from the I2C interface (Table 2). Connecting WP to GND
increases the supply current by 19.6A (max).
To ensure a fail-safe, write-protect feature, write the
data to be protected to both the nonvolatile and volatile
registers before pulling WP high. Releasing WP (WP =
0) and sending partial or invalid I2C commands (such
as single-byte address polling) can load the volatile
ADDRESS BYTE
COMMAND BYTE
DATA BYTE
1
2
3
4
5
6
7
8
9
10 111213 14 15 1617
18
19 20 212223 24 25 26
27
SCL CYCLE
NUMBER
START
(S)
A6 A5 A4 A3 A2 A1 A0
ACK
(A)
TX NV V R3 R2 R1 R0
ACK
(A)
D7 D6 D5 D4 D3 D2 D1 D0
ACK
(A)
STOP
(P)
NOTES
VREG
0101 A2 A1 A0 0
0
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
NVREG
0101 A2 A1 A0 0
0
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
NVREGxVREG
0101 A2 A1 A0 0
0
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
VREGxNVREG
0101 A2 A1 A0 0
0
1
0
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
WIPER A
ONLY
VREG
0101 A2 A1 A0 0
0
1
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
NVREG
0101 A2 A1 A0 0
0
1
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
NVREGxVREG
0101 A2 A1 A0 0
0
1
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
VREGxNVREG
0101 A2 A1 A0 0
0
1
0
1
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
WIPER B
ONLY
VREG
0101 A2 A1 A0 0
0
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
NVREG
0101 A2 A1 A0 0
0
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
NVREGxVREG
0101 A2 A1 A0 0
0
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
VREGxNVREG
0101 A2 A1 A0 0
0
1
0
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
WIPERS
A AND B
Table 3. Command Byte Summary
COMMAND
WP = 0
WP = 1
Write to VREG
I2C data is written to VREG.
Wiper position updates with I2C data.
No change to NVREG.
Copy NVREG to VREG.
Wiper position updates with NVREG data.
No change to NVREG.
Write to NVREG
No change to VREG or wiper position.
I2C data is written to NVREG.
No change to VREG or wiper position.
No change to NVREG.
Copy NVREG to VREG
Copy NVREG to VREG.
Wiper position updates with NVREG data.
No change to NVREG.
Copy NVREG to VREG.
Wiper position updates with NVREG data.
No change to NVREG.
Copy VREG to NVREG
Copy VREG to NVREG.
No change to VREG or wiper position.
No change to NVREG.
Table 2. Write-Protect Behavior of VREG and NVREG
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