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參數(shù)資料
| 型號： | MAX547 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Octal, 13-Bit Voltage-Output DAC with Parallel Interface(八通道,并行,電壓輸出,13位D/A轉(zhuǎn)換器) |
| 中文描述： | 八通道、13位、電壓輸出DAC，并行接口 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 276K |
| 代理商： | MAX547 |
Analog Ground for DAC E and DAC F
_______________Detailed Desc ription
Analog S ec tion
The MAX547 contains eight 13-bit, voltage-output
DACs. These DACs are “inverted” R-2R ladder net-
works that convert 13-bit digital inputs into equivalent
analog output voltages, in proportion to the applied ref-
erence voltages. The MAX547 has one reference input
(REF_) and one analog-ground input (AGND_) for each
pair of DACs. The four REF_ inputs allow different full-
scale output voltages for each DAC pair, and the four
AGND_ inputs allow different offset voltages for each
DAC pair.
The DAC ladder outputs are buffered with op amps that
operate with a gain of two. The inverting node of the
amplifier is connected to the respective reference
input, resulting in bipolar output voltages from -REF_ to
4095/4096 REF_. Figure 1 shows the simplified DAC
circuit.
M
Oc tal, 13-Bit Voltage-Output
DAC with Parallel Interfac e
_______________________________________________________________________________________
7
_________________________________________________Pin Desc ription (c ontinued)
FLAT
PACK
10
PLCC
NAME
FUNCTION
36
REFGH
Reference Voltage Input for DAC G and DAC H. Bypass to AGNDGH with a 0.1μF to 1μF capacitor.
30
16
A2
Address Bit 2
38
VOUTH
DAC H Output Voltage
33
–———–
Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
G and H to the respective DAC latches.
32
35
AGNDGH
Analog Ground for DAC G and DAC H
34
GND
Digital Ground
PIN
27
29
28
41
VOUTE
DAC E Output Voltage
35
39
VOUTG
DAC G Output Voltage
33
40
VOUTF
DAC F Output Voltage
34
44
AGNDEF
38
Figure 1. DAC Simplified Circuit Diagram
2R
2R
R
D0
D10
D11
D12
R
R
R
R
OUT
REF–
AGND–
2R
2R
2R
V
DAC
43
REFEF
Reference Voltage Input for DAC E and DAC F. Bypass to AGNDEF with a 0.1μF to 1μF capaci-
37
32
–———
Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
E and F to the respective DAC latches.
26
17
A1
Address Bit 1
11
18
A0
Address Bit 0
19–31
D12–D0
Data Bits 12–0
13–25
12
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