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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MAX547ACMH+T |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 15/16闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC DAC 13BIT OCTAL PAR 44-MQFP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 500 |
| 瑷�(sh猫)缃檪(sh铆)闁擄細 | 5µs |
| 浣嶆暩(sh霉)锛� | 13 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 骞惰伅(li谩n) |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 8 |
| 闆诲闆绘簮锛� | 闆� ± |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 889mW |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 44-QFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 44-MQFP锛�10x10锛� |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� | 8 闆诲锛屽柈妤�锛�8 闆诲锛岄洐妤� |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | * |
Reference and Analog-Ground Inputs
The REF_ inputs can range between AGND_ and VDD.
However, the DAC outputs will operate to VDD - 0.6V
and VSS + 0.6V, due to the output amplifiers鈥� voltage-
swing limitations. The AGND_ inputs can be offset by
any voltage within the supply rails. The offset-voltage
potential must be lower than the reference-voltage
potential. For more information, refer to the
Digital Code
and
Analog Output Voltage section in the Applications
Information.
The input impedance of the REF_ inputs is code depen-
dent. It is at its lowest value (5k
min) when the input
code of the referring DAC pair is 0 1010 1010 1010
(0AAAhex). Its maximum value, typically 50k
, occurs
when the code is 0000hex. When all reference inputs are
driven from the same source, the minimum load imped-
ance is 1.25k
. Since the input impedance at REF_ is
code dependent, load regulation of the reference used is
important. For more information, see
Reference
Selection in the Applications Information section.
The input capacitance at REF_ is also code dependent,
and typically varies from 125pF to 300pF. Its minimum
value occurs when the code of the referring DAC pair is
set to all 0s. It is at its maximum value with all 1s on both
DACs.
Output Buffer Amplifiers
The MAX547鈥檚 voltage outputs are internally buffered
by precision gain-of-two amplifiers with a typical slew
rate of 3V/s. With a full-scale transition at its output,
the typical settling time to 卤12LSB is 5s when loaded
with 10k
in parallel with 50pF, or 6s when loaded
with 10k
in parallel with 100pF.
Digital Inputs and Interface Logic
All digital inputs are compatible with both TTL and
CMOS logic. The MAX547 interfaces with microproces-
sors using a data bus at least 13 bits wide. The inter-
face is double buffered, allowing simultaneous update
of all DACs. There are two latches for each DAC (see
Functional Diagram): an input latch that receives data
from the data bus, and a DAC latch that receives data
from the input latch. Address lines A0, A1, and A2
select which DAC鈥檚 input latch receives data from the
data bus, as shown in Table 1. Transfer data from the
input latches to the DAC latches by asserting the asyn-
chronous LD_ signal. Each DAC鈥檚 analog output
reflects the data held in its DAC latch. All control inputs
are level triggered.
Data can be latched or transferred directly to the DAC.
CS and WR control the input latch and LD_ transfers
information from the input latch to the DAC latch. The
input latch is transparent when CS and WR are low, and
the DAC latch is transparent when LD_ is low. The
address lines (A0, A1, A2) must be valid throughout the
time CS and WR are low (Figure 3). Otherwise, the data
can be inadvertently written to the wrong DAC. Data is
latched within the input latch when either CS or WR is
high. Taking LD_ high latches data into the DAC latches.
If LD_ is brought low when WR and CS are low, it must
be held low for t3 or longer after WR and CS are high
(Figure 3).
Pulling the asynchronous CLR input low sets all DAC
outputs to a nominal 0V, regardless of the state of CS,
WR, and LD_. Taking CLR high latches 1000hex into
all input latches and DAC latches.
Table 1. MAX547 DAC Addressing
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
8
_______________________________________________________________________________________
TO INPUT LATCH OF DAC H
TO INPUT LATCH OF DAC G
TO INPUT LATCH OF DAC F
TO INPUT LATCH OF DAC E
TO INPUT LATCH OF DAC D
TO INPUT LATCH OF DAC C
TO INPUT LATCH OF DAC B
TO INPUT LATCH OF DAC A
TO DAC LATCHES OF DAC G AND DAC H
TO DAC LATCHES OF DAC E AND DAC G
TO DAC LATCHES OF DAC C AND DAC D
TO DAC LATCHES OF DAC C AND DAC B
TO ALL INPUT AND DAC LATCHES
A2
A1
A0
LDGH
LDEF
LDCD
LDAB
CLR
WR
CS
Figure 2. Input Control Logic
A0
A2
FUNCTION
0
DAC A input latch
1
0
DAC D input latch
1
0
DAC B input latch
0
DAC C input latch
0
A1
0
1
0
1
DAC E input latch
1
DAC F input latch
1
0
1
DAC G input latch
1
DAC H input latch
1
鐩搁棞(gu膩n)PDF璩囨枡 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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| MAX547ACQH | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:- Rail/Tube 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪: |
| MAX547ACQH+D | 鍔熻兘鎻忚堪:鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒- DAC 13-Bit 8Ch Precision DAC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)閲�:1 DAC 杓稿嚭绔暩(sh霉)閲�:1 杞�(zhu菐n)鎻涢€熺巼:2 MSPs 鍒嗚鲸鐜�:16 bit 鎺ュ彛椤炲瀷:QSPI, SPI, Serial (3-Wire, Microwire) 绌�(w臎n)瀹氭檪(sh铆)闁�:1 us 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:SOIC-14 灏佽:Tube |
| MAX547ACQH+TD | 鍔熻兘鎻忚堪:鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒- DAC 13-Bit 8Ch Precision DAC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)閲�:1 DAC 杓稿嚭绔暩(sh霉)閲�:1 杞�(zhu菐n)鎻涢€熺巼:2 MSPs 鍒嗚鲸鐜�:16 bit 鎺ュ彛椤炲瀷:QSPI, SPI, Serial (3-Wire, Microwire) 绌�(w臎n)瀹氭檪(sh铆)闁�:1 us 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:SOIC-14 灏佽:Tube |
| MAX547ACQH-D | 鍔熻兘鎻忚堪:鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒- DAC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)閲�:1 DAC 杓稿嚭绔暩(sh霉)閲�:1 杞�(zhu菐n)鎻涢€熺巼:2 MSPs 鍒嗚鲸鐜�:16 bit 鎺ュ彛椤炲瀷:QSPI, SPI, Serial (3-Wire, Microwire) 绌�(w臎n)瀹氭檪(sh铆)闁�:1 us 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:SOIC-14 灏佽:Tube |
| MAX547ACQH-TD | 鍔熻兘鎻忚堪:鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒- DAC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)閲�:1 DAC 杓稿嚭绔暩(sh霉)閲�:1 杞�(zhu菐n)鎻涢€熺巼:2 MSPs 鍒嗚鲸鐜�:16 bit 鎺ュ彛椤炲瀷:QSPI, SPI, Serial (3-Wire, Microwire) 绌�(w臎n)瀹氭檪(sh铆)闁�:1 us 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:SOIC-14 灏佽:Tube |
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