參數(shù)資料
型號: MAX547BCQH+D
廠商: Maxim Integrated Products
文件頁數(shù): 14/16頁
文件大?。?/td> 0K
描述: IC DAC OCTL V-OUT 13BIT 44-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 28
設(shè)置時間: 5µs
位數(shù): 13
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 8
電壓電源: 雙 ±
功率耗散(最大): 1.07W
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 管件
輸出數(shù)目和類型: 8 電壓,單極;8 電壓,雙極
采樣率(每秒): *
產(chǎn)品目錄頁面: 1395 (CN2011-ZH PDF)
Analog Ground for DAC E and DAC F
_______________Detailed Description
Analog Section
The MAX547 contains eight 13-bit, voltage-output
DACs. These DACs are “inverted” R-2R ladder net-
works that convert 13-bit digital inputs into equivalent
analog output voltages, in proportion to the applied ref-
erence voltages. The MAX547 has one reference input
(REF_) and one analog-ground input (AGND_) for each
pair of DACs. The four REF_ inputs allow different full-
scale output voltages for each DAC pair, and the four
AGND_ inputs allow different offset voltages for each
DAC pair.
The DAC ladder outputs are buffered with op amps that
operate with a gain of two. The inverting node of the
amplifier is connected to the respective reference
input, resulting in bipolar output voltages from -REF_ to
4095/4096 REF_. Figure 1 shows the simplified DAC
circuit.
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
_______________________________________________________________________________________
7
_________________________________________________Pin Description (continued)
FLAT
PACK
PLCC
NAME
FUNCTION
36
REFGH
Reference Voltage Input for DAC G and DAC H. Bypass to AGNDGH with a 0.1F to 1F capacitor.
30
16
A2
Address Bit 2
38
VOUTH
DAC H Output Voltage
33
L
D
G
H
Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
G and H to the respective DAC latches.
32
35
AGNDGH
Analog Ground for DAC G and DAC H
34
GND
Digital Ground
PIN
10
27
29
28
41
VOUTE
DAC E Output Voltage
35
39
VOUTG
DAC G Output Voltage
33
40
VOUTF
DAC F Output Voltage
34
44
AGNDEF
38
Figure 1. DAC Simplified Circuit Diagram
2R
R
D0
D10
D11
D12
RR
OUT
REF–
AGND–
2R
VDAC
43
REFEF
Reference Voltage Input for DAC E and DAC F. Bypass to AGNDEF with a 0.1F to 1F capaci-
37
32
L
D
E
F
Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
E and F to the respective DAC latches.
26
17
A1
Address Bit 1
11
18
A0
Address Bit 0
19–31
D12–D0
Data Bits 12–0
13–25
12
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