參數(shù)資料
型號(hào)： MAX5499ETE+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 16/20頁(yè)
文件大?。?/td> 0K
描述： IC DIG POT 10BIT 16-TQFN-EP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
接片： 1024
電阻（歐姆）： 50k
電路數(shù)： 2
溫度系數(shù)： 標(biāo)準(zhǔn)值 35 ppm/°C
存儲(chǔ)器類型： 非易失
接口： 3 線串行（芯片選擇）
電源電壓： 2.5 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-WQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 16-TQFN-EP（5x5）
包裝： 帶卷 (TR)
MAX5494–MAX5499
10-Bit, Dual, Nonvolatile, Linear-Taper
Digital Potentiometers
_______________________________________________________________________________________
5
TIMING CHARACTERISTICS
(VDD = +2.7V to +5.25V, VSS = GND = 0, VH_ = VDD, VL_ = 0, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
VDD = +5.0V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG SECTION
MAX5494/MAX5498
5
Wiper Settling Time (Note 6)
tS
MAX5495/MAX5499
22
s
SPI-COMPATIBLE SERIAL INTERFACE (Figure 6)
SCLK Frequency
fSCLK
7
MHz
SCLK Clock Period
tCP
140
ns
SCLK Pulse-Width High
tCH
60
ns
SCLK Pulse-Width Low
tCL
60
ns
CS Fall to SCLK Rise Setup
tCSS
60
ns
SCLK Rise to CS Rise Hold
tCSH
0ns
DIN to SCLK Setup
tDS
40
ns
DIN Hold After SCLK
tDH
0ns
SCLK Rise to CS Fall Delay
tCS0
15
ns
CS Rise to SCLK Rise Hold
tCS1
60
ns
CS Pulse-Width High
tCSW
150
ns
Write NV Register Busy Time
tBUSY
12
ms
Note 1: 100% production tested at TA = +25°C and TA = +85°C. Guaranteed by design to TA = -40°C.
Note 2: The DNL and INL are measured for the voltage-divider with H_ = VDD and L_ = VSS. The wiper terminal (W_) is unloaded
and measured with a high-input-impedance voltmeter.
Note 3: The DNL and INL are measured with L_ = VSS = 0. For VDD = 5V, the wiper terminal is driven with a current source of IW =
80A for the 50k device and IW = 400A for the 10k device. For VDD = 3V, the wiper terminal is driven with a current
source of IW = 40A for the 50k device and IW = 200A for the 10k device.
Note 4: The wiper resistance is measured using the source currents given in Note 3.
Note 5: The device draws higher supply current when the digital inputs are driven with voltages between (VDD - 0.5V) and (GND +
0.5V). See the Supply Current vs. Digital Input Voltage graph in the
Typical Operating Characteristics.
Note 6: Wiper settling test condition uses the voltage-divider with a 10pF load on W_. Transition code from 0 to 495 and measure
the time from CS going high to the wiper voltage settling to within 0.5% of its final value.
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