參數(shù)資料
型號: MAX5511
廠商: Maxim Integrated Products, Inc.
英文描述: +1.8V to +5.5V. Ultra-Low-Power. 8-Bit. Voltage-Output DACs
中文描述: +1.8V至+5.5V、超低功耗、8位、電壓輸出DAC
文件頁數(shù): 11/18頁
文件大?。?/td> 1012K
代理商: MAX5511
M
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
______________________________________________________________________________________
11
Detailed Description
The MAX5510/MAX5511 single, 8-bit, ultra-low-power,
voltage-output DACs offer Rail-to-Rail buffered voltage
outputs. The DACs operate from a 1.8V to 5.5V supply
and require only 6μA (max) supply current. These
devices feature a shutdown mode that reduces overall
current, including the reference input current, to just
0.18μA. The MAX5511 includes an internal reference
that saves additional board space and can source up
to 8mA, making it functional as a system reference. The
16MHz, 3-wire serial interface is compatible with SPI,
QSPI, and MICROWIRE protocols. When V
DD
is
applied, all DAC outputs are driven to zero scale with
virtually no output glitch. The MAX5510/MAX5511 out-
put buffers are configured in force sense allowing users
to externally set voltage gains on the output (an output-
amplifier inverting input is available). These devices
come in a 4mm x 4mm thin QFN package.
Digital Interface
The MAX5510/MAX5511 use a 3-wire serial interface
compatible with SPI, QSPI, and MICROWIRE protocols
(Figures 1 and 2).
The MAX5510/MAX5511 include a single, 16-bit, input
shift register. Data loads into the shift register through
the serial interface.
CS
must remain low until all 16 bits
are clocked in. Data loads MSB first, D9–D0. The 16
bits consist of 4 control bits (C3–C0), 8 data bits
(D7–D0), and 4 sub-bits. (see Table 1). D7–D0 are the
DAC data bits and S3–S0 are the sub-bits. The sub-bits
must be set to zero for proper operation. The control
bits C3–C0 control the MAX5510/MAX5511, as outlined
in Table 2.
Each DAC channel includes two registers: an input reg-
ister and a DAC register. The input register holds input
data. The DAC register contains the data updated to
the DAC output.
The double-buffered register configuration allows any
of the following:
Loading the input registers without updating the DAC
registers
Updating the DAC registers from the input registers
Updating all the input and DAC registers simultaneously
8-BIT DAC
2-BIT
PROGRAMMABLE
REFERENCE
DAC
REGISTER
OUT
REF
BUF
GND
MAX5511
REFOUT
INPUT
REGISTER
POWER-
DOWN
CONTROL
CONTROL
LOGIC
AND
SHIFT
REGISTER
FB
SCLK
V
DD
DIN
CS
MAX5511 Functional Diagram
相關(guān)PDF資料
PDF描述
MAX5510ETC Replaced by SN55462 : Dual High-Voltage, High-Current Peripheral Drivers 8-CDIP -55 to 125
MAX5511ETC Replaced by SN55462 : Dual High-Voltage, High-Current Peripheral Drivers 8-CDIP -55 to 125
MAX5530ETC ULTRA-LOW POWER, 12-BIT, VOLTAGE-OUTPUT DACS
MAX5531ETC ULTRA-LOW POWER, 12-BIT, VOLTAGE-OUTPUT DACS
MAX5547 Dual, 10-Bit, Current-Sink Output DAC
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