參數(shù)資料
型號: MAX5530ETC
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: ULTRA-LOW POWER, 12-BIT, VOLTAGE-OUTPUT DACS
中文描述: SERIAL INPUT LOADING, 660 us SETTLING TIME, 12-BIT DAC, QCC12
封裝: 4 X 4 MM, 0.80 MM HEIGHT, MO-220, QFN-12
文件頁數(shù): 18/19頁
文件大小: 1015K
代理商: MAX5530ETC
M
Ultra-Low-Power, 12-Bit,
Voltage-Output DACs
18
______________________________________________________________________________________
Power Supply and Bypassing
Considerations
Bypass the power supply with a 0.1μF capacitor to GND.
Minimize lengths to reduce lead inductance. If noise
becomes an issue, use shielding and/or ferrite beads to
increase isolation. For the thin QFN package, connect
the exposed paddle to ground.
Layout Considerations
Digital and AC transient signals coupling to GND can
create noise at the output. Use proper grounding tech-
niques, such as a multilayer board with a low-inductance
ground plane. Wire-wrapped boards and sockets are not
recommended. For optimum system performance, use
printed circuit (PC) boards. Good PC board ground lay-
out minimizes crosstalk between DAC outputs, reference
inputs, and digital inputs. Reduce crosstalk by keeping
analog lines away from digital lines.
Figure 8. Bipolar Output Circuit
Figure 9. Separate Force-Sense Outputs Create Unity and
Greater-than-Unity DAC Gains Using the Same Reference
REFIN
MAX5530
OUT
V
OUT
FB
V+
10k
10k
V-
DAC
REFIN
V
OUT
OUT
MAX5530
FB
R2
R1
DAC
Figure 10. Software-Configurable Output Gain
H
L
FB
W
N
DAC
IS THE NUMERIC VALUE OF THE DAC INPUT CODE.
N
POT
IS THE NUMERIC VALUE OF THE POT INPUT CODE.
REFIN
MAX5530
MAX5401
SOT-POT
100k
VOUT
5PPM/
°
C
RATIOMETRIC
TEMPCO
1.8V
V
DD
5.5V
V
OUT
OUT
= V
REFIN
×
N
DAC
V
POT
)
1 + 255 - N
SCLK
DIN
CS2
CS1
DAC
Chip Information
TRANSISTOR COUNT: 10,688
PROCESS: BiCMOS
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