參數(shù)資料
型號(hào): MAX5547ETA+T
廠商: Maxim Integrated Products
文件頁數(shù): 12/12頁
文件大?。?/td> 0K
描述: IC DAC 10BIT DUAL 8-TDFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時(shí)間: 10µs
位數(shù): 10
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-WDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 8-TDFN-EP(3x3)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): *
Set
CS low to begin clocking input data at DIN on the
falling edge of SCLK (see Figure 1). Serial communica-
tions to the shift register consist of a 16-bit command
word loaded from DIN. The first four control bits
(C3–C0) determine the target register (see Table 1).
The next 10 data bits set the current-sink level. D9 is
the MSB and D0 the LSB. Set bits S1 and S0 to zero for
proper operation. Data is latched into the appropriate
DAC register on the 16th SCLK falling edge. After writ-
ing 16 bits, drive
CS high. Keep CS low throughout the
entire 16-bit word.
Write the command word to configure DAC registers A
and B individually or both registers at the same time.
The command word also determines whether the DACs
use the internal or external reference.
The MAX5547 powers up in external reference mode with
DAC registers A and B set to IFS = 1.2mA at code 000h.
Applications Information
Power Sequencing
Ensure the voltages applied at REF, OUTA, and OUTB
do not exceed VDD at any time. If proper power
sequencing is not possible, connect an external
Schottky diode between REF/OUTA/OUTB and VDD to
ensure compliance with the absolute maximum ratings.
Power-Supply Bypassing and Ground
Management
Digital or AC transient signals on GND create noise at
the analog output. Return GND to the highest quality
ground plane available. For extremely noisy environ-
ments, bypass both REF and VDD to GND with 10F
and 0.1F capacitors in parallel, with the 0.1F capaci-
tor as close to the device as possible. Careful PC
board ground layout minimizes crosstalk between the
DAC outputs and digital inputs.
MAX5547
Dual, 10-Bit, Current-Sink Output DAC
_______________________________________________________________________________________
9
CS
SCLK
tCSS
tDS
tDH
tCL
tCH
C3
C2
S1
S0
tCP
tCSH
tCSW
DIN
Figure 1. SPI Serial-Interface Timing Diagram
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