參數(shù)資料
型號(hào): MAX5556ESA+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 17/17頁(yè)
文件大?。?/td> 0K
描述: IC DAC STEREO AUDIO 8-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 16
數(shù)據(jù)接口: I²S,串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
輸出數(shù)目和類(lèi)型: 2 電壓,單極
采樣率(每秒): 50k
MAX5556
Low-Cost Stereo Audio DAC
9
Maxim Integrated
Clock and Data Interface
The MAX5556 strobes serial data (SDATA) in on the ris-
ing edge of SCLK. LRCLK routes data to the left or right
outputs and, along with SCLK, defines the number of
bits per sample transferred. The digital interpolators fil-
ter data at internal clock rates derived from the MCLK
frequency. Each device supports both internal and
external serial clock (SCLK) modes.
SDATA Input
The serial interface strobes data (SDATA) in on the ris-
ing edge of SCLK, MSB first. The MAX5556 supports
four different data formats, as detailed in Figure 4.
Serial Clock (SCLK)
SCLK strobes the individual data bits at SDATA into the
DAC. The MAX5556 operates in one of two modes:
internal serial clock mode or external serial clock mode.
External SCLK Mode
The MAX5556 operates in external serial clock mode
when SCLK activity is detected. The device returns to
internal serial clock mode if no SCLK signal is detected
for one LRCLK period. Figure 5 details the external serial
clock mode timing parameters.
MSB
LSB
-2
-3
-4 -5
+5
+4
+3
+2
+1
-1
-2
-3
-4
+5
+4
+3
+2
+1
LRCLK
SCLK
SDATA
DATA DIRECTED TO OUTL
-1
INTERNAL SERIAL CLOCK MODE
EXTERNAL SERIAL CLOCK MODE
I2S, 16-BIT DATA AND INTERNAL SCLK =
32 x fS IF MCLK/ LRCLK = 256 OR 512
I2S, UP TO 24 BITS OF DATA AND INTERNAL
SCLK = 48 X fS IF MCLK/ LRCLK = 384
I2S, UP TO 24 BITS OF DATA
DATA VALID ON RISING EDGE OF SCLK
DATA DIRECTED TO OUTR
Figure 4. MAX5556 Data Format Timing
tSLRH
tSLRS
tSDH
SDATA
SCLK
LRCLK
tSDS
tSCLKL
tSCLKH
tSCLK
Figure 5. External SCLK Serial Timing Diagram
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