參數(shù)資料
型號(hào): MAX5742EUB
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: 12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface
中文描述: SERIAL INPUT LOADING, 4 us SETTLING TIME, 12-BIT DAC, PDSO10
封裝: 5 X 3 MM, MO-187CBA, MICRO, SOP-10
文件頁數(shù): 10/15頁
文件大?。?/td> 676K
代理商: MAX5742EUB
M
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
10
______________________________________________________________________________________
write sequence is initiated on a falling edge of
CS
. Not
keeping
CS
low during the first 15 SCLK cycles dis-
cards input data. The serial clock (SCLK) can idle
either high or low between transitions.
The MAX5742 has two internal registers per DAC, the
input register and the DAC register. The input register
holds the data that is waiting to be shifted to the DAC
register. All input registers can be loaded without
updating the output. This function is useful when all out-
puts need to be updated at the same time. The input
register can be made transparent. When the input reg-
ister is transparent, the data written into DIN loads
directly to the DAC register and the output is updated.
The DAC output is not updated until data is written to
the DAC register. See Table 2 for a list of serial-inter-
face programming commands.
Power-On Reset (POR)
The MAX5742 has an internal POR circuit. At power-up all
DACs are powered-down and OUT_ is terminated to
GND through 100k
resistors. Contents of input and DAC
registers are cleared to all zero. An 8μs recovery time
after issuing a wake-up command is needed before writ-
ing to the DAC registers. Power-down mode control com-
mands can be applied immediately with no recovery time.
C3-C0 are control bits. The data bits D11 to D0 are in
straight binary format. All zeros correspond to zero
scale and all ones correspond to full scale.
Digital Inputs
The digital inputs are compatible with CMOS logic. In
order to save power and reduce input to output coupling,
SCLK and DIN input buffers are powered down immedi-
ately after completion of shifting 16 bits into the input shift
register. A high to low transition at
CS
powers up SCLK
and DIN input buffers.
EXTENDED
CONTROL
DATA BITS
C3
1
1
1
1
C2
1
1
1
1
C1
1
1
1
1
C0
1
1
1
1
D11
D5
X
X
X
X
D4
0
0
0
0
D3
0
0
0
0
D2
0
0
0
0
D1
0
0
1
1
D0
0
1
0
1
DESCRIPTION
FUNCTION
DAC A
DAC A
DAC A
DAC A
DAC O/P, wakeup
Floating output
Output is terminated with 1k
Output is terminated with 100k
DAC O/P, wakeup
Floating output
Output is terminated with 1k
Output is terminated with 100k
DAC O/P, wakeup
Floating output
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
1
0
1
0
1
DAC B
DAC B
DAC B
DAC B
DAC C
DAC C
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
DAC C
DAC C
DAC D
DAC D
DAC D
DAC D
Output is terminated with 1k
Output is terminated with 100k
DAC O/P, wakeup
Floating output
Output is terminated with 1k
Output is terminated with 100k
DAC O/P, wakeup
Floating output
Output is terminated with 1k
Output is terminated with 100k
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
DAC A-D
DAC A-D
DAC A-D
DAC A-D
Table 1. Power-Down Mode Control
X = Don’t care
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