參數(shù)資料
型號: MAX5774UTK+T
廠商: Maxim Integrated Products
文件頁數(shù): 5/28頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 32CH V-OUT 68-TQFN
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
設置時間: 20µs
位數(shù): 14
數(shù)據接口: 串行
轉換器數(shù)目: 32
電壓電源: 模擬和數(shù)字
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-TQFN 裸露焊盤
供應商設備封裝: 68-TQFN-EP(10x10)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 32 電壓,單極
采樣率(每秒): *
MAX5773/MAX5774/MAX5775
32-Channel, 14-Bit, Voltage-Output
DACs with Serial Interface
______________________________________________________________________________________
13
MAX5773/MAX5774/MAX5775
Pin Description
PIN
68 TQFN
64 TQFP
NAME
FUNCTION
1, 16, 34, 35, 36,
51, 52, 53, 68
15, 33, 34,
49, 64
N.C.
No Connection. Not internally connected.
2, 50, 59
1, 48, 55
AVCC
Output-Amplifier Positive Supply Input. Bypass to AGND with a 0.1F capacitor.
3
2
OUT9
DAC9 Buffered Analog Output Voltage
4
3
OUT8
DAC8 Buffered Analog Output Voltage
5
4
OUT7
DAC7 Buffered Analog Output Voltage
6
5
I.C.
Internally Connected. Do not make any connections to I.C.
7
6
OUT6
DAC6 Buffered Analog Output Voltage
8
7
OUT5
DAC5 Buffered Analog Output Voltage
9
8
OUT4
DAC4 Buffered Analog Output Voltage
10, 46
9, 44
AGND
Analog Ground
11
10
OUT3
DAC3 Buffered Analog Output Voltage
12, 33, 47
11, 32, 45
VSS
Bypass to AGND with a 0.1F capacitor
13
12
OUT2
DAC2 Buffered Analog Output Voltage
14
13
OUT1
DAC1 Buffered Analog Output Voltage
15
14
OUT0
DAC0 Buffered Analog Output Voltage
17, 25
16, 24
DVDD
Digital Power-Supply Input. Bypass to DGND with a 0.1F capacitor.
18, 26
17, 25
DGND
Digital Ground
19
18
GS2
Ground-Sense Analog Input 2. Offsets the DAC amplifier outputs OUT0, OUT1,
OUT2, OUT16, OUT17, and OUT18 by ±0.5V to compensate for a remote system
ground potential difference.
20
19
DSP
Digital Serial-Interface Mode-Select Input. Drive low for DSP interface mode. Drive
high for SPI interface mode.
21
20
CS
Active-Low Digital Chip-Select Input
22
21
DOUT
Digital Serial Data Output. Use DOUT to daisy chain or read the contents of the
internal registers. DOUT data clocks out on the falling edge of SCLK, MSB first.
23
22
SCLK
Digital Serial Clock Input
24
23
DIN
Digital Serial Data Input. Data clocks in on the falling edge of SCLK.
27
26
LDAC
Active-Low Digital Load DAC Input. Drive this asynchronous input low to transfer the
contents of the input register to their respective DAC registers and update all DAC
outputs accordingly.
28
27
RESET
Active-Low Reset Input. Drive this asynchronous input low to initiate a power-on
reset. See the Power-On Reset section for further information.
29
28
GS1
Ground-Sense Analog Input 1. Offsets the DAC amplifier outputs OUT3–OUT15 and
OUT19–OUT31 by ±0.5V to compensate for a remote system ground potential
difference.
30, 60
29, 56
REFGND
Reference Ground
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