參數(shù)資料
型號: MAX5841LEUB+T
廠商: Maxim Integrated Products
文件頁數(shù): 9/15頁
文件大?。?/td> 0K
描述: IC DAC 10BIT QUAD 2WIRE 10-UMAX
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
設置時間: 4µs
位數(shù): 10
數(shù)據(jù)接口: 串行
轉換器數(shù)目: 4
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 10-µMAX
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 4 電壓,單極
采樣率(每秒): *
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5k
, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are
at VDD = +5V, TA = 25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Hysteresis
0.05
VDD
V
Input Leakage Current
Digital inputs = 0 or VDD
±0.1
±1A
Input Capacitance
6pF
DIGITAL OUTPUT (SDA)
Output Logic Low Voltage
VOL
ISINK = 3mA
0.4
V
Three-State Leakage Current
IL
Digital inputs = 0 or VDD
±0.1
±1A
Three-State Output Capacitance
6pF
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
SR
0.5
V/s
Voltage Output Settling Time
To 1/2LSB code 100 hex to 300 hex or 300
hex to 100 hex (Note 5)
412
s
Digital Feedthrough
Code = 000 hex, digital inputs from 0 to VDD
0.2
nV-s
Digital-to-Analog Glitch Impulse
Major carry transition (code = 1FF hex to
200 hex and 200 hex to 1FF hex)
12
nV-s
DAC-to-DAC Crosstalk
2.4
nV-s
POWER SUPPLIES
Supply Voltage Range
VDD
2.7
5.5
V
All digital inputs at 0 or VDD = 3.6V
230
395
Supply Current with No Load
IDD
All digital inputs at 0 or VDD = 5.5V
280
420
A
Power-Down Supply Current
IDDPD
All digital inputs at 0 or VDD = 5.5V
0.3
1
A
TIMING CHARACTERISTICS (FIGURE 1)
Serial Clock Frequency
fSCL
0
400
kHz
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
s
START Condition Hold Time
tHD,STA
0.6
s
SCL Pulse Width Low
tLOW
1.3
s
SCL Pulse Width High
tHIGH
0.6
s
Repeated START Setup Time
tSU,STA
0.6
s
Data Hold Time
tHD,DAT
0
0.9
s
Data Setup Time
tSU,DAT
100
ns
SDA and SCL Receiving Rise
Time
tr
(Note 5)
0
300
ns
SDA and SCL Receiving Fall Time
tf
(Note 5)
0
300
ns
SDA Transmitting Fall Time
tf
(Note 5)
20 +
0.1Cb
250
ns
STOP Condition Setup Time
tSU,STO
0.6
s
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