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參數(shù)資料
| 型號： | MAX5887EGK+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/18頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 3.3V 500MSPS 68-QFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 11ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 130mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 68-QFN 裸露焊盤（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 500M |
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
16
______________________________________________________________________________________
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed at
the package bottom surface, facing the PC board side
of the package. This allows a solid attachment of the
package to the PC board with standard infrared (IR)
flow soldering techniques. A specially created land pat-
tern on the PC board, matching the size of the EP (6mm
6mm), ensures the proper attachment and grounding
of the DAC. Designing vias*** into the land area and
implementing large ground planes in the PC board
design allow for highest performance operation of the
DAC. An array of at least 4 4 vias (
≤0.3mm diameter
per via hole and 1.2mm pitch between via holes) is rec-
ommended for this 68-pin QFN-EP package.
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best straight line fit
(closest approximation to the actual transfer curve) or a
line drawn between the end points of the transfer func-
tion, once offset and gain errors have been nullified. For
a DAC, the deviations are measured at every individual
step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function.
Offset Error
The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full scale of the
DAC. This error affects all codes by the same amount.
FERRITE BEAD
AVCC
1
F10F47F
ANALOG POWER-SUPPLY SOURCE
FERRITE BEAD
DVCC
1
F10F47F
DIGITAL POWER-SUPPLY SOURCE
FERRITE BEAD
VCLK
1
F10F47F
CLOCK POWER-SUPPLY SOURCE
AVCC
AGND
MAX5887
B0–B13
14
0.1
F
DGND
0.1
F
VCLK
CLKGND
0.1
F
OUTP
OUTN
DVDD
BYPASSING—DAC LEVEL
BYPASSING—BOARD LEVEL
Figure 13. Recommended Power-Supply Decoupling and Bypassing Circuitry
***Vias connect the land pattern to internal or external copper planes. It is important to connect as many vias as possible to the analog
ground plane to minimize inductance.
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| MAX5888AEGK-D | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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