參數(shù)資料
型號(hào): MAX5889EVKIT#
廠商: Maxim Integrated Products
文件頁數(shù): 2/16頁
文件大小: 0K
描述: KIT EVALUATION FOR MAX5889
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
DAC 的數(shù)量: 1
位數(shù): 12
采樣率(每秒): 600M
數(shù)據(jù)接口: 并聯(lián)
設(shè)置時(shí)間: 11ns
DAC 型: 電流
工作溫度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: MAX5889
MAX5889
Clock Inputs (CLKP, CLKN)
To achieve the best possible jitter performance, the
MAX5889 features flexible differential clock inputs
(CLKP, CLKN) that operate from a separate clock
power supply (AVCLK). Drive the differential clock
inputs from a single-ended or a differential clock
source. For highest dynamic performance, differential
clock source is required. For single-ended operation,
drive CLKP and bypass CLKN to CGND.
CLKP and CLKN are internally biased at AVCLK / 2,
allowing the AC-coupling of clock sources directly to
the device without external resistors to define the DC
level. The input resistance from CLKP and CLKN to
ground is approximately 5k.
Data-Timing Relationship
Figure 3 shows the timing relationship between digital
LVDS data, clock, and output signals. The MAX5889
features a 2ns hold, a -1.2ns setup, and a 2.5ns propa-
gation delay time. There is a 5.5 clock-cycle latency
between data write operation and the corresponding
analog output transition.
LVDS Data Inputs
The MAX5889 has 12 pairs of LVDS data inputs (offset
binary format) and can accept data rates up to
600MWps. Each differential input pair is terminated with
an internal 110 resistor. The common-mode input
resistance is 3.2k.
Power-Down Operation (PD)
The MAX5889 features a power-down mode that
reduces the DAC’s power consumption. Set PD high to
power down the MAX5889. Set PD low or leave uncon-
nected for normal operation.
When powered down, the MAX5889 overall power con-
sumption is reduced to less than 13W. The MAX5889
requires 350s to wake up from power-down and enter
a fully operational state if the external reference is
used. If the internal reference is used, the power-down
recovery time is 10ms. The PD internal pulldown circuit
sets the MAX5889 in normal mode when PD is left
unconnected.
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
10
______________________________________________________________________________________
IOUT
OUTN OUTP
CURRENT
SOURCES
CURRENT
SWITCHES
AVDD3.3
Figure 2. Simplified Analog Output Structure
D0–D11
tSETUP
tHOLD
DN
CLKP
CLKN
DN + 2
DN + 4
DN + 6
IOUTP
IOUTN
tPD
DN + 1
DN + 3
DN + 5
DN + 7
OUTN - 2
OUTN - 3
OUTN - 4
OUTN - 5
OUTN - 6
OUTN - 7
OUTN-1
OUTN
Figure 3. Timing Relationship Between Clock, Input Data, and Analog Output
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