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| 型號(hào)： | MAX5895 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs |
| 中文描述： | 16位、500Msps、插值與調(diào)制、雙路DAC，CMOS輸入 |
| 文件頁(yè)數(shù)： | 10/32頁(yè) |
| 文件大?。?/td> | 807K |
| 代理商： | MAX5895 |
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M
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
10
______________________________________________________________________________________
Pin Description
PIN
1
2
3, 4, 5
NAME
CLKP
CLKN
N.C.
FUNCTION
Noninverting Differential Clock Input
Inverting Differential Clock Input
Internally Connected. Do not connect.
6, 21, 30, 37
DV
DD1.8
Digital Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to ground with a
0.1μF capacitor as close to the pin as possible.
7–12, 15–20,
22–25
A15–A0
A-Port Data Inputs.
Dual-port mode:
I-channel data input. Data is latched on the rising/falling edge (programmable) of the DATACLK.
Single-port mode:
I-channel and Q-channel data input, with SELIQ.
13, 44
DV
DD3.3
CMOS I/O Power Supply. Accepts a 3.0V to 3.6V supply range. Bypass each pin to ground with a
0.1μF capacitor as close to the pin as possible.
14
DATACLK
Programmable Data Clock Input/Output. See the
DATACLK Modes
section for details.
26
SELIQ/B15
Select I/Q-Channel Input or B-Port MSB Input.
Single-port mode:
If SELIQ = LOW, data is latched into Q-channel on the rising/falling edge (programmable) of
the DATACLK.
If SELIQ = HIGH, data is latched into I-channel on the rising/falling edge (programmable) of the
DATACLK.
Dual-port mode:
Q-channel MSB input.
27
DATACLK/B14
Alternate DATACLK Input/Output or B-Port Bit 14 Input.
Single-port mode:
See the
DATACLK Modes
section for details.
Dual-port mode:
Q-channel bit 14 input.
If unused connect to GND.
28, 29, 31–36,
38–43
B13–B0
B-Port Data Bits 13–0.
Dual-port mode:
Q-channel inputs. Data is latched on the rising/falling (programmable) edge of the DATACLK.
Single-port mode:
Connect to GND.
45
46
47
48
49
50
SDO
SDI
SCLK
CS
RESET
REFIO
Serial-Port Data Output
Serial-Port Data Input
Serial-Port Clock Input. Data on SDI is latched on the rising edge of SCLK.
Serial-Port Interface Select. Drive
CS
low to enable serial-port interface.
Reset Input. Set
RESET
low during power-up.
Reference Input/Output. Bypass to ground with a 1μF capacitor as close to the pin as possible.
51
DACREF
Current-Set Resistor Return Path. For a 20mA full-scale output current, connect a 2k
resistor
between FSADJ and DACREF. Internally connected to GND.
Do not use as an external ground
connection.
52
FSADJ
Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA full-
scale output current, connect a 2k
resistor between FSADJ and DACREF.
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