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參數(shù)資料
| 型號： | MAX5941ACSE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 20/24頁 |
| 文件大小： | 0K |
| 描述： | IC IEEE 802.3AF-COMP POE 16-SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 控制器類型： | 以太網(wǎng)供電控制器（POE） |
| 接口： | IEEE 802.3af |
| 電源電壓： | 48V |
| 電流 - 電源： | 1mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
MAX5941A/MAX5941B
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
_______________________________________________________________________________________
5
IIN
IINi +1
IINi
IOFFSET
dRi
1V
VINi
VINi +1
IOFFSET
IINi -
VINi
dRi
(VINi + 1 - VINi)
=
1V
(IINi + 1 - IINi)
Figure 1. Effective Differential Input Resistance/Offset Current
Note 1:
All min/max limits for the PD interface are production tested at +85°C (extended grade)/+70°C (commercial grade). Limits
at +25°C and -40°C are guaranteed by design. All PWM controller min/max limits are 100% production tested at +25°C
and +85°C (extended grade)/+70°C (commercial grade). Limits at -40°C are guaranteed by design, unless otherwise
noted.
Note 2:
The input offset current is illustrated in Figure 1.
Note 3:
Effective differential input resistance is defined as the differential resistance between GND and VEE without any external
resistance.
Note 4:
Classification current is turned off whenever the IC is in power mode.
Note 5:
See Table 2 in the PD Classification Mode section. RDISC and RCL must be 100ppm or better.
Note 6:
See Thermal Dissipation section for details.
Note 7:
When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5k
(±1%), the turn-
on threshold set point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO
pin does not exceed its maximum rating of 8V when VIN is at the maximum voltage.
Note 8:
When the VUVLO is below VTH, G, UVLO, the MAX5941 sets the turn-on voltage threshold internally (VUVLO,ON).
Note 9:
An input voltage or VUVLO glitch below their respective thresholds shorter than or equal to tOFF_DLY does not cause the
MAX5941A/MAX5941B to exit power-on mode (as long as the input voltage remains above an operable voltage level of 12V).
Note 10: PGOOD references to OUT while PGOOD references to VEE.
Note 11: Guaranteed by design.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX5941AESE | 功能描述:電源開關 IC - POE / LAN RoHS:否 制造商:Fairchild Semiconductor 開關數(shù)量:Single 開關配置:SPST 開啟電阻（最大值）:7.3 Ohms 串話: 帶寬: 開啟時間（最大值）:13 ns 關閉時間（最大值）:20 ns 切換電壓（最大）: 工作電源電壓:8 V to 26 V 最大工作溫度:+ 125 C 安裝風格:Through Hole 封裝 / 箱體:TO-220F-6 |
| MAX5941AESE+ | 功能描述:輸入/輸出控制器接口集成電路 IEEE 802.3af POE Int/PWM Controller RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| MAX5941AESE+T | 功能描述:輸入/輸出控制器接口集成電路 IEEE 802.3af POE Int/PWM Controller RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| MAX5941AESE-T | 功能描述:電源開關 IC - POE / LAN RoHS:否 制造商:Fairchild Semiconductor 開關數(shù)量:Single 開關配置:SPST 開啟電阻（最大值）:7.3 Ohms 串話: 帶寬: 開啟時間（最大值）:13 ns 關閉時間（最大值）:20 ns 切換電壓（最大）: 工作電源電壓:8 V to 26 V 最大工作溫度:+ 125 C 安裝風格:Through Hole 封裝 / 箱體:TO-220F-6 |
| MAX5941BCSE | 功能描述:電源開關 IC - POE / LAN RoHS:否 制造商:Fairchild Semiconductor 開關數(shù)量:Single 開關配置:SPST 開啟電阻（最大值）:7.3 Ohms 串話: 帶寬: 開啟時間（最大值）:13 ns 關閉時間（最大值）:20 ns 切換電壓（最大）: 工作電源電壓:8 V to 26 V 最大工作溫度:+ 125 C 安裝風格:Through Hole 封裝 / 箱體:TO-220F-6 |
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