參數(shù)資料
型號(hào)： MAX6310EUK34D3+T
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
封裝： LEAD FREE, MO-178AA, SOT-23, 5 PIN
文件頁(yè)數(shù)： 9/10頁(yè)
文件大?。?/td> 216K
代理商： MAX6310EUK34D3+T
M
4A Ultra-Low-Input-Voltage
LDO Regulators
_______________________________________________________________________________________
9
Thermal Considerations
in PCB Layout
How much power the package can dissipate strongly
depends on the mounting method of the IC to the PCB
and the copper area for cooling. Using the JEDEC test
standard, the maximum power dissipation allowed in
the package is 2667mW. This data is obtained with
+70°C ambient temperature and +150°C maximum
junction temperature. The test board has dimensions of
3in x 3in with four layers of 2oz copper and FR-4 mater-
ial with 62mil finished thickness. Nine thermal vias are
used under the thermal paddle with a diameter of 12mil
and 1mil plated copper thickness. Top and bottom lay-
ers are used to route the traces. Two middle layers are
solid copper and isolated from the nine thermal vias.
More power dissipation can be handled by the pack-
age if great attention is given during PCB layout. For
example, using the top and bottom copper as a
heatsink and connecting the thermal vias to one of the
middle layers (GND) transfers the heat from the pack-
age into the board more efficiently, resulting in lower
junction temperature at high power dissipation in some
MAX8556/MAX8557 applications. Furthermore, the sol-
der mask around the IC area on both top and bottom
layers can be removed to radiate the heat directly into
the air. The maximum allowable power dissipation in
the IC is as follows:
where T
J(MAX)
is the maximum junction temperature
(+150°C), T
A
is the ambient air temperature,
θ
JC
(1.7°C/W for the 16-pin TQFN) is the thermal resistance
from the junction to the case, and
θ
CA
is the thermal
resistance from the case to the surrounding air through
the PCB, copper traces, and the package materials.
θ
CA
is directly related to system level variables and can
be modified to increase the maximum power dissipa-
tion. The TQFN package has an exposed thermal pad
on its underside. This pad provides a low thermal resis-
tance path for heat transfer into the PCB. This low ther-
mally resistive path carries a majority of the heat away
from the IC. The PCB is effectively a heatsink for the IC.
The exposed paddle should be connected to a large
ground plane for proper thermal and electrical perfor-
mance. The minimum size of the ground plane is
dependent upon many system variables. To create an
efficient path, the exposed paddle should be soldered
to a thermal landing, which is connected to the ground
plane by thermal vias. The thermal landing should be at
least as large as the exposed paddle and can be made
larger depending on the amount of free space from the
exposed paddle to the other pin landings.
A sample layout is available on the MAX8556 evalua-
tion kit to speed designs.
P
T
T
MAX
J MAX
JC
θ
A
CA
θ
(
(
)
)
=
+
PACKAGE TYPE
16 TQFN-EP
PACKAGE CODE
T1655+2
DOCUMENT NO.
Chip Information
相關(guān)PDF資料
PDF描述
MB1-120-01-S-01-SL 20 CONTACT(S), FEMALE, RIGHT ANGLE SINGLE PART CARD EDGE CONN, SURFACE MOUNT
MB1-120-01-S-02-SL 20 CONTACT(S), FEMALE, RIGHT ANGLE SINGLE PART CARD EDGE CONN, SURFACE MOUNT
MB1-130-01-S-01-SL 30 CONTACT(S), FEMALE, RIGHT ANGLE SINGLE PART CARD EDGE CONN, SURFACE MOUNT
MB1-130-01-S-02-SL 30 CONTACT(S), FEMALE, RIGHT ANGLE SINGLE PART CARD EDGE CONN, SURFACE MOUNT
MB1-140-01-S-01-SL 40 CONTACT(S), FEMALE, RIGHT ANGLE SINGLE PART CARD EDGE CONN, SURFACE MOUNT
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MAX6310EUK35D3-T 功能描述:監(jiān)控電路 5-Pin Multiple-Input Programmable Reset ICs RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開(kāi)關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
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