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參數(shù)資料
| 型號(hào)： | MAX6324_UT__-T |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | レP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset |
| 中文描述： | レP監(jiān)控電路與窗口（最小/最大）看門狗和手動(dòng)復(fù)位 |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 226K |
| 代理商： | MAX6324_UT__-T |
M
μP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
6
_______________________________________________________________________________________
Detailed Description
The MAX6323/MAX6324 μP supervisory circuits main-
tain system integrity by alerting the μP to fault condi-
tions. In addition to a standard V
CC
monitor (for
power-on reset, brownout detect, and power-down
reset), the devices include a sophisticated watchdog
timer that detects when the processor is running out-
side an expected window of operation for a specific
application. The watchdog signals a fault when the
input pulses arrive too early (faster than the selected
t
WD1
timeout period) or too late (slower than the select-
ed t
WD2
timeout period) (Figure 1). Incorrect timing can
lead to poor or dangerous system performance in tight-
ly controlled operating environments. Incorrect timing
could be the result of improper μP clocking or code
execution errors. If a timing error occurs, the
MAX6323/MAX6324 issue a watchdog pulse output,
independent from the reset output, indicating that sys-
tem maintenance may be required.
Watchdog Function
A pulse on the watchdog output
WDPO
can be trig-
gered by a fast fault or a slow fault. If the watchdog
input (WDI) has two falling edges too close to each
other (faster than t
WD1
) (Figure 2) or falling edges that
are too far apart (slower than t
WD2
) (Figure 3),
WDPO
is
pulsed low. Normal watchdog operation is displayed in
Figure 4 (
WDPO
is not asserted). The internal watch-
dog timer is cleared when a WDI falling edge is detect-
ed within the valid watchdog window or when the
device’s
RESET
or
WDPO
outputs are deasserted. All
WDI input pulses are ignored while either
RESET
or
WDPO
is asserted. Figure 1 identifies the input timing
regions where
WDPO
fault outputs will be observed
with respect to t
WD1
and t
WD2
. After
RESET
or
WDPO
deasserts, the first WDI falling edge is ignored for the
fast fault condition (Figure 2).
Upon detecting a watchdog fault, the
WDPO
output will
pulse low for 1ms.
WDPO
is an open-drain output.
Connect a pullup resistor on
WDPO
to any supply up to
+6V.
V
CC
Reset
The MAX6323/MAX6324 also include a standard V
CC
reset monitor to ensure that the μP is started in a known
state and to prevent code execution errors during
power-up, power-down, or brownout conditions.
RESET
is asserted whenever the V
CC
supply voltage
*UNDETERMINED STATES MAY OR MAY NOT GENERATE A FAULT CONDITION.
POSSIBLE STATES
GUARANTEED TO
ASSERT WDPO
GUARANTEED TO
ASSERT WDPO
GUARANTEED NOT TO
ASSERT WDPO
FAST FAULT
CONDITION 1
SLOW FAULT
CONDITION 3
NORMAL OPERATION
CONDITION 2
t
WD1
(min)
)
t
WD1
(max)
t
WD2
(min)
t
WD2
(max)
*UNDETERMINED
*UNDETERMINED
Figure 1. Detailed Watchdog Input Timing Relationship
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