參數(shù)資料
型號(hào): MAX6452UT17L-T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): 電源管理
英文描述: µP Reset Circuits with Long Manual Reset Setup Period
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO6
封裝: ROHS COMPLIANT, SOT-23, 6 PIN
文件頁(yè)數(shù): 9/13頁(yè)
文件大小: 158K
代理商: MAX6452UT17L-T
MAX6443–MAX6452
P Reset Circuits with Long Manual Reset
Setup Period
_______________________________________________________________________________________
5
Detailed Description
Reset Output
The reset output is typically connected to the reset
input of a microprocessor (P). A P’s reset input starts
or restarts the P in a known state. The MAX6443–
MAX6452 P supervisory circuits provide the reset
logic to prevent code-execution errors during power-
up, power-down and brownout conditions (see the
Typical Operating Circuit).
RESET changes from high to low whenever the moni-
tored voltages (RSTIN or VCC) drop below the reset
threshold voltages. Once VRSTIN and VCC exceed their
respective reset threshold voltages, RESET remains low
for the reset timeout period and then goes high. RESET
is one-shot pulsed whenever selected manual reset
inputs are asserted. RESET stays asserted for the nor-
mal reset timeout period (140ms min).
RESET is guaranteed to be in the proper output logic
state for VCC inputs ≥ 1V. For applications requiring valid
reset logic when VCC is less than 1V, see the Ensuring a
Valid RESET Output Down to VCC = 0V section.
Pin Description
PIN
MAX6443
MAX6444
MAX6445
MAX6446
MAX6447
MAX6448
MAX6449
MAX6450
MAX6451
MAX6452
NAME
FUNCTION
1
2
GND
Ground
21
11
1
RESET
Active-Low Push-Pull or Open-Drain Output. RESET
changes from high to low when VCC or RSTIN drops below
its selected reset threshold and remains low for the 210ms
reset timeout period after all monitored power-supply inputs
exceed their selected reset thresholds. RESET is one-shot
pulsed low for the reset timeout period (140ms min) after
selected manual reset inputs are asserted longer than the
specified setup period. For the open-drain output, use a
minimum 20k
pullup resistor to VCC .
3—3—3
Manual Reset Input, Active Low. Internal 50k
pullup to
VCC. Pull MR1 low for the typical input pulse width (tMR)
to one-shot pulse RESET for the reset timeout period.
—3
MR1
Manual Reset Input, Active Low. Pull both MR1 and
MR2 low for the typical input pulse width (tMR) to one-
shot pulse RESET for the reset timeout period.
44
4
VCC
VCC Voltage Input. Power supply and input for the
primary microprocessor voltage reset monitor.
—5
—6
MR2
Manual Reset Input, Active Low. Internal 50k
pullup to
VCC. Pull both MR1 and MR2 low for the typical input
pulse width (tMR) to one-shot pulse RESET for the reset
timeout period.
——
5
6
MR2
Manual Reset Input. Pull the MR2 high to immediately
one-shot pulse RESET for the reset timeout period.
RSTIN
Reset Input. High-impedance input to the adjustable
reset comparator. Connect RSTIN to the center point of
an external resistor-divider to set the threshold of the
externally monitored voltage.
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