參數(shù)資料
型號(hào)： MAX6697EP
廠商： Maxim Integrated Products, Inc.
英文描述： 7-Channel Precision Temperature Monitor
中文描述： 7通道高精度溫度監(jiān)測(cè)
文件頁(yè)數(shù)： 3/19頁(yè)
文件大?。?/td> 252K
代理商： MAX6697EP
M
7-Channel Precision Temperature Monitor
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +5.5V, T
A
= -40
°
C to +125
°
C, unless otherwise noted. Typical values are at V
CC
= +3.3V and T
A
= +25
°
C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SMBus INTERFACE (SCL, SDA)
Logic Input Low Voltage
V
IL
0.8
V
V
V
μA
V
pF
V
CC
= 3.0V
V
CC
= 5.0V
2.2
2.4
-1
Logic Input High Voltage
V
IH
Input Leakage Current
Output Low Voltage
Input Capacitance
SMBus-COMPATIBLE TIMING (Figures 3 and 4) (Note 2)
Serial Clock Frequency
+1
0.3
V
OL
C
IN
I
SINK
= 6mA
5
f
SCL
(Note 3)
f
SCL
= 100kHz
f
SCL
= 400kHz
f
SCL
= 100kHz
f
SCL
= 400kHz
90% of SCL to 90% of SDA,
f
SCL
= 100kHz
400
kHz
4.7
1.6
4.7
0.6
Bus Free Time Between STOP
and START Condition
t
BUF
μs
START Condition Setup Time
μs
0.6
Repeat START Condition Setup
Time
t
SU:STA
90% of SCL to 90% of SDA,
f
SCL
= 400kHz
10% of SDA to 90% of SCL
0.6
μs
START Condition Hold Time
t
HD:STA
0.6
μs
90% of SCL to 90% of SDA,
f
SCL
= 100kHz
4
STOP Condition Setup Time
t
SU:STO
90% of SCL to 90% of SDA,
f
SCL
= 400kHz
10% to 10%, f
SCL
= 100kHz
10% to 10%, f
SCL
= 400kHz
90% to 90%
f
SCL
= 100kHz
f
SCL
= 400kHz (Note 4)
f
SCL
= 100kHz
f
SCL
= 400kHz
f
SCL
= 100kHz
f
SCL
= 400kHz
0.6
μs
1.3
1.3
0.6
300
Clock Low Period
t
LOW
μs
Clock High Period
t
HIGH
μs
Data Hold Time
t
HD:DAT
900
ns
250
100
Data Setup Time
t
SU:DAT
ns
1
Receive SCL/DSA Rise Time
t
R
0.3
300
50
45
μs
Receive SCL/SDA Fall Time
Pulse Width of Spike Suppressed
SMBus Timeout
t
F
t
SP
ns
ns
ms
0
25
t
TIMEOUT
SDA low period for interface reset
37
Note 1:
All parameters are tested at T
A
= +25
°
C. Specifications over temperature are guaranteed by design.
Note 2:
Timing specifications are guaranteed by design.
Note 3:
The serial interface resets when SCL is low for more than t
TIMEOUT
.
Note 4:
A transition must internally provide at least a hold time to bridge the undefined region (300ns max) of SCL
’
s falling edge.
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