參數(shù)資料
型號: MAX6730AUTRD1+T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: Single-/Dual-/Triple-Voltage µP Supervisory Circuits with Independent Watchdog Output
中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO6
封裝: LEAD FREE, MO-178AB, SOT-23, 6 PIN
文件頁數(shù): 4/21頁
文件大?。?/td> 2018K
代理商: MAX6730AUTRD1+T
MAX6730A–MAX6735A
Threshold Overdrive graph, for which reset pulses are
not generated. The graph was produced using falling
VCC_ pulses, starting above VTH and ending below the
reset threshold by the magnitude indicated (reset
threshold overdrive). The graph shows the maximum
pulse width that a falling VCC transient typically might
have without causing a reset pulse to be issued. As the
amplitude of the transient increases (i.e., goes further
below the reset threshold), the maximum allowable
pulse width decreases. A 0.1F bypass capacitor
mounted close to VCC_ provides additional transient
immunity.
Watchdog Software Considerations
Setting and resetting the watchdog input at different
points in the program rather than “pulsing” the watch-
dog input high-low-high or low-high-low helps the
watchdog timer closely monitor software execution.
This technique avoids a “stuck” loop, in which the
watchdog timer continues to be reset within the loop,
preventing the watchdog from timing out. Figure 6
shows an example flow diagram in which the I/O dri-
ving the watchdog input is set high at the beginning of
the program, set low at the beginning of every subrou-
tine or loop, and then set high again when the program
returns to the beginning. If the program “hangs” in any
subroutine, the I/O continually asserts low (or high),
and the watchdog timer expires, issuing a reset or
interrupt.
Single-/Dual-/Triple-Voltage P Supervisory
Circuits with Independent Watchdog Output
12
______________________________________________________________________________________
START
SET WDI
HIGH
PROGRAM
CODE
RETURN
SUBROUTINE
COMPLETED
HANG IN
SUBROUTINE
SUBROUTINE OR
PROGRAM LOOP
SET WDI LOW
Figure 6. Watchdog Flow Diagram
MAX6730A–
MAX6735A
VREF
RESET
TIMEOUT
PERIOD
RESET
OUTPUT
DRIVER
WATCHDOG
TIMER
REF
VCC1
VREF / 2
GND
VCC1
MR
VCC1
VCC2
MR
PULLUP
VCC1
VCC2
RSTIN
RST
WDO
WDI
Functional Diagram
相關(guān)PDF資料
PDF描述
MAX6730AUTRD2+T Single-/Dual-/Triple-Voltage µP Supervisory Circuits with Independent Watchdog Output
MAX6730AUTRD3+ Single-/Dual-/Triple-Voltage µP Supervisory Circuits with Independent Watchdog Output
MAX6730AUTRD3+T Single-/Dual-/Triple-Voltage µP Supervisory Circuits with Independent Watchdog Output
MAX6730AUTRD4+T Single-/Dual-/Triple-Voltage µP Supervisory Circuits with Independent Watchdog Output
MAX6730AUTRD5+T Single-/Dual-/Triple-Voltage µP Supervisory Circuits with Independent Watchdog Output
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