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參數(shù)資料
| 型號(hào)： | MAX6847KARD3-T |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | Low-Power, Adjustable Battery Monitors with Hysteresis and Integrated µP Reset |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | MO-178, SOT-23, 8 PIN |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 257K |
| 代理商： | MAX6847KARD3-T |
MAX6846–MAX6849
Low-Power, Adjustable Battery Monitors with
Hysteresis and Integrated P Reset
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 1.6V to 5.5V, VCC = 1.2V to 5.5V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LBO, LBOL, LBOH Output
Open-Drain Leakage Current
Output deasserted
500
nA
MAX68_ _ _ _ T
3.000
3.075
3.150
MAX68_ _ _ _ S
2.850
2.925
3.000
MAX68_ _ _ _ R
2.550
2.625
2.700
MAX68_ _ _ _ Z
2.250
2.313
2.375
MAX68_ _ _ _ Y
2.125
2.188
2.250
MAX68_ _ _ _ W
1.620
1.665
1.710
VCC Reset Threshold
VTH
MAX68_ _ _ _ V
1.530
1.575
1.620
V
VCC Reset Hysteresis
0.3
%
VCC to RESET Delay
tRD
VCC falling at 10mV/s from (VTH + 100mV)
to (VTH - 100mV)
50
s
MAX68_ _ _ _ _ D3
150
225
300
VCC to RESET Timeout Period
tRP
MAX68_ _ _ _ _ D7
1200
1800
2400
ms
VIL
0.3 x VCC
MR Input Voltage
VIH
0.7 x VCC
V
MR Minimum Pulse Width
tMPW
1s
MR Glitch Rejection
100
ns
MR to RESET Delay
200
ns
MR Reset Timeout Period
tMRP
150
225
300
ms
MR Pullup Resistance
MR to VCC
750
1500
2250
MR Rising Debounce Period
tDEB
(Note 3)
150
225
300
ms
VCC
≥ 1.53V, ISOURCE = 100A, RESET
deasserted
0.8 x VCC
RESET Output High
(Push-Pull)
VOH
VCC
≥ 2.55V, ISOURCE = 500A, RESET
deasserted
0.8 x VCC
V
VCC
≥ 1.0V, ISINK = 50A, RESET asserted
0.3
VCC
≥ 1.2V, ISINK = 100A, RESET asserted
0.3
RESET Output Low
VOL
VCC
≥ 2.12V, ISINK = 1.2mA, RESET
asserted
0.3
V
RESET Output Leakage Current
(Open Drain)
RESET deasserted
500
nA
Note 1: Production testing done at TA = +25°C; limits over temperature guaranteed by design only.
Note 2: The device is powered up by the highest voltage between VDD and VCC.
Note 3: MR input ignores falling input pulses, which occur within the MR debounce period (tDEB) after a valid MR reset assertion.
This prevents invalid reset assertion due to switch bounce.
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