參數(shù)資料
型號(hào): MAX6872ETJ
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors with Charge-Pump Outputs
中文描述: 6-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC32
封裝: 7 X 7 MM, 0.80 MM HEIGHT, MO-220, TQFN-32
文件頁(yè)數(shù): 8/48頁(yè)
文件大?。?/td> 374K
代理商: MAX6872ETJ
MR
The manual reset (MR) input initiates a reset condi-
tion. Register 40h determines the programmable out-
puts that assert while MR is low (Table 6). All affected
programmable outputs remain asserted (see the
Programmable Outputs section) for their PO_ timeout
periods after MR releases high. An internal 10A cur-
rent source pulls MR to DBP. Leave MR unconnected
or connect to DBP if unused. A programmable output
cannot depend solely on MR.
MARGIN
MARGIN allows system-level testing while power sup-
plies exceed the normal ranges. Registers 41h and
42h determine whether the programmable outputs
assert to a predetermined state or hold the last state
as MARGIN is driven low (Table 7). Drive MARGIN low
to set the programmable outputs in a known state
while system-level testing occurs. Leave MARGIN
unconnected or connect to DBP if unused. An internal
10A current source pulls MARGIN to DBP. The state
of each programmable output does not change while
MARGIN = GND. MARGIN overrides MR if both assert
at the same time.
Programmable Outputs
The MAX6872 features eight programmable outputs,
while the MAX6873 features five programmable outputs.
Selectable output-stage configurations include: active low
or active high, open drain, weak pullup, push-pull, or
charge pump. During power-up, the programmable out-
puts pull to GND with an internal 10A current sink for 1V
< VABP < VUVLO. The programmable outputs remain in
their active states until their respective PO_ timeout peri-
ods expire, and all of the programmed conditions are met
for each output. Any output programmed to depend on
no condition always remains in its active state (Table 20).
An active-high configured output is considered asserted
MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
16
______________________________________________________________________________________
Table 5. GPI1–GPI4 Active Logic States
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
[0]
GPI1. 0 = active low. 1 = active high.
[1]
GPI2. 0 = active low. 1 = active high.
[2]
GPI3. 0 = active low. 1 = active high.
3Bh
803Bh
[3]
GPI4. 0 = active low. 1 = active high.
Table 6. Programmable Output Behavior and MR
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT
RANGE
DESCRIPTION
[0]
PO1 (MAX6872 only). 0 = PO1 independent of MR. 1 = PO1 asserts when MR = low.
[1]
PO2 (MAX6872 only). 0 = PO2 independent of MR. 1 = PO2 asserts when MR = low.
[2]
PO3 (MAX6872)/PO1 (MAX6873). 0 = PO3/PO1 independent of MR.
1 = PO3/PO1 asserts when MR = low.
[3]
PO4 (MAX6872)/PO2 (MAX6873). 0 = PO4/PO2 independent of MR.
1 = PO4/PO2 asserts when MR = low.
[4]
PO5 (MAX6872)/PO3 (MAX6873). 0 = PO5/PO3 independent of MR.
1 = PO5/PO3 asserts when MR = low.
[5]
PO6 (MAX6872)/PO4 (MAX6873). 0 = PO6/PO4 independent of MR.
1 = PO6/PO4 asserts when MR = low.
[6]
PO7 (MAX6872)/PO5 (MAX6873). 0 = PO7/PO5 independent of MR.
1 = PO7/PO5 asserts when MR = low.
40h
8040h
[7]
PO8 (MAX6872 only). 0 = PO8 independent of MR. 1 = PO8 asserts when MR = low.
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