參數(shù)資料
型號: MAX6882ETE+T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: Dual-/Triple-Voltage, Power-Supply Sequencers/Supervisors
中文描述: POWER SUPPLY SUPPORT CKT, QCC24
封裝: 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, TQFN-16
文件頁數(shù): 13/19頁
文件大?。?/td> 401K
代理商: MAX6882ETE+T
MAX6880–MAX6883
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
_______________________________________________________________________________________
3
Note 1: Specifications guaranteed for the stated global conditions. 100% production tested at TA = +25°C and TA = +85°C.
Specifications at TA = -40°C to +85°C are guaranteed by design. These devices meet the parameters specified when at
least one of IN1/IN2/IN3 is between 2.7V to 5.5V, while the remaining IN1/IN2/IN3 are between 0 and 5.5V.
Note 2: A current ID = 2.5A ±15% is generated internally and is used to set the DELAY and TIMEOUT periods and used as a refer-
ence for tDELAY and tTIMEOUT.
Note 3: The total DELAY is tDELAY = 200s + (500k x CDELAY). Leave DELAY unconnected for 200s delay. The total TIMEOUT is
tTIMEOUT = 200s + (500k x CTIMEOUT). Leave TIMEOUT unconnected for 200s timeout.
Note 4: A current IS = 25A ±10% is generated internally and used as a reference for tFAULT, tRETRY, and slew rate.
Note 5: During power-up, only the condition OUT_ < ramp - VTRK is checked in order to stop the ramp. However, both conditions
OUT_ < ramp – VTRK_F and OUT_ > ramp + VTRK_F cause a fault. During power-down, only the condition OUT > ramp +
VTRK is checked in order to stop the ramp. However, both conditions OUT_ < ramp - VTRK_F and OUT_ > ramp + VTRK_F
cause a fault (see Figure 10). Therefore, if OUT1, OUT2, and OUT3 (during power-up tracking and power-down) differ by
more than 2 x VTRK_F, a fault condition is asserted.
Note 6: A 100 pulldown to GND activated by a fault condition. See the Internal Pulldown section.
ELECTRICAL CHARACTERISTICS (continued)
(IN1, IN2, or IN3 = +2.7V to +5.5V, EN/UV = MARGIN = ABP, TA = -40°C to +85°C, unless otherwise specified. Typical values are
at TA = +25°C, unless otherwise noted.) (Note 1)
Power-Good Threshold
VTH_PG
VOUT_ falling
91.5
92.5
93.5
%
Power-Good Threshold Hysteresis
VHYS_PG
VOUT_ rising
0.5
%
GATE_ Output High
VGOH
ISOURCE = 0.5A
IN_ +
4.2
IN_ +
5.0
IN_ +
5.8
V
GATE_ Pullup Current
IGUP
During power-up and power-down,
VGATE_ = 1V
2.5
4
A
IGD
During power-up and power-down,
VGATE_ = 5V
2.5
4
A
When disabled, VGATE_ = 5V, VIN_
≥ 2.7V
9.5
GATE_ Pulldown Current
IGDS
When disabled, VGATE_ = 5V, VIN_
≥ 4V
20
mA
SET_ to GATE_ Delay
tD-GATE
SET falling, 25mV overdrive
10
s
VIN_
≥ 2.7V, ISINK = 1mA, output asserted
0.3
PG/RST Output Low
VOL
VIN_
≥ 4.0V, ISINK = 4mA, output asserted
0.4
V
Tracking Differential Voltage Stop
Ramp
VTRK
Differential between each of the OUT_ and
the ramp voltage during power-up and
power-down, Figure 1 (Note 5)
75
125
180
mV
Tracking Differential Fault Voltage
VTRK_F
Differential between each of the OUT_ and
the ramp voltage, Figure 1 (Note 5)
200
250
310
mV
Power-Low Threshold
VTH_PL
OUT_ falling
125
142
170
mV
Power-Low Hysteresis
VTH_PLHYS OUT_ rising
10
mV
OUT to GND Pulldown Impedance
IN_ > 2.7V (Note 6)
100
MARGIN Pullup Current
IIN
710
13
A
VIL
0.8
MARGIN Input Voltage
VIH
2.0
V
MARGIN Glitch Rejection
100
ns
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