參數(shù)資料
型號: MAX7300ANI
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 其它接口
英文描述: 2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander
中文描述: SPECIALTY INTERFACE CIRCUIT, PDIP28
封裝: PLASTIC, DIP-28
文件頁數(shù): 10/22頁
文件大?。?/td> 348K
代理商: MAX7300ANI
M
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
10
______________________________________________________________________________________
Operation with Multiple Masters
If the MAX7300 is operated on a 2-wire interface with
multiple masters, a master reading the MAX7300 should
use a repeated start between the write, which sets the
MAX7300
s address pointer, and the read(s) that takes
the data from the location(s). This is because it is possi-
ble for master 2 to take over the bus after master 1 has
set up the MAX7300
s address pointer, but before
master 1 has read the data. If master 2 subsequently
changes, the MAX7300
s address pointer, then master
1
s delayed read can be from an unexpected location.
Command Address Autoincrementing
Address autoincrementing allows the MAX7300 to be
configured with the shortest number of transmissions
by minimizing the number of times the command
address needs to be sent. The command address
stored in the MAX7300 generally increments after each
data byte is written or read (Table 4).
Initial Power-Up
On initial power-up, all control registers are reset and
the MAX7300 enters shutdown mode (Table 6).
Transition (Port Data Change) Detection
Port transition detection allows seven maskable ports
P24 to P30 to be continuously monitored for changes in
their logic status (Figure 10). Enable transition detec-
tion by setting the M bit in the configuration register
(Table 9) after setting the mask register. If port 31 is
configured as an output (Tables 1 and 2), then P31
automatically becomes an interrupt request (IRQ) out-
put to flag detected transitions. Port 31 can be config-
ured and used as a general-purpose input port instead,
if not required for use as the IRQ output.
The mask register determines which of the seven ports
P24 to P30 are monitored (Table 10). Set the appropri-
ate mask bit to enable that port for transition detect.
Clear the mask bit if transitions on that port are to be
ignored by the transition detection logic. Ports are mon-
itored regardless of their I/O configuration, both input
and output.
SCL
SDA
BY TRANSMITTER
CLOCK PULSE FOR ACKNOWLEDGMENT
START CONDITION
SDA
BY RECEIVER
1
2
8
9
S
Figure 5. Acknowledge
SDA
SCL
1
0
A3
A2
A1
A0
0
MSB
LSB
R/W
ACK
Figure 6. Slave Address
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