參數(shù)資料
型號(hào): MAX7310AUE+
廠商: Maxim Integrated Products
文件頁數(shù): 9/15頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 8B 16TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 96
接口: I²C,SM 總線
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時(shí)鐘: 400kHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
包括: POR
MAX7310
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
_______________________________________________________________________________________
3
Note 1: All parameters are 100% production tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Minimum SCL clock frequency is limited by the MAX7310 bus timeout feature, which resets the serial bus interface if either
SDA or SCL is held low for a 30ms minimum.
Note 3: A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIL of the SCL signal) in
order to bridge the undefined region of SCL’s falling edge.
Note 4: tF measured between 90% to 10% of V+.
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
DC ELECTRICAL CHARACTERISTICS (continued)
(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Leakage Current
-1
+1
A
Input Capacitance
10
pF
AC ELECTRICAL CHARACTERISTICS
(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, TA = -40°C to +125°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
fSCL
(Note 2)
400
kHz
BUS Timeout
tTIMEOUT
30
60
ms
Bus Free Time Between STOP
and START Condition
tBUF
Figure 2
1.3
s
Hold Time (Repeated) START
Condition
tHD, STA
Figure 2
0.6
s
Repeated START Condition Setup
Time
tSU, STA
Figure 2
0.6
s
STOP Condition Setup Time
tSU, STO
Figure 2
0.6
s
Data Hold Time
tHD, DAT
Figure 2 (Note 3)
0.9
s
Data Setup Time
tSU, DAT
Figure 2
0.1
s
SCL Low Period
tLOW
Figure 2
1.3
s
SCL High Period
tHIGH
Figure 2
0.7
s
SCL/SDA Fall Time (Transmitting)
tF
Figure 2 (Note 4)
250
ns
Pulse Width of Spike Supressed
tSP
(Note 5)
50
ns
PORT TIMING
Output Data Valid
tPV
Figure 9
1
s
Input Data Setup Time
tPS
Figure 10
29
s
Input Data Hold Time
tPH
Figure 10
0
s
RESET
Reset Pulse Width
100
ns
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