參數(shù)資料
型號(hào)： MAX7319ATE+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 16/16頁(yè)
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 8B 16TQFN-EP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
接口： I²C
輸入/輸出數(shù)： 8
中斷輸出： 是
頻率 - 時(shí)鐘： 400kHz
電源電壓： 1.71 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 16-TQFN-EP（3x3）
包裝： 帶卷 (TR)
SDA operates as both an input and an open-drain out-
put. A pullup resistor, typically 4.7k
Ω, is required on
SDA. SCL operates only as an input. A pullup resistor,
typically 4.7k
Ω, is required on SCL if there are multiple
masters on the 2-wire interface, or if the master in a sin-
gle-master system has an open-drain SCL output.
Each transmission consists of a START condition sent
by a master, followed by the MAX7319’s 7-bit slave
address plus R/W bit, then 1 or more data bytes, and
finally a STOP condition (Figure 2).
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, the master
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 2).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 3).
Acknowledge
The acknowledge bit is a clocked 9th bit the recipient
uses to acknowledge receipt of each byte of data
(Figure 4). Each byte transferred effectively requires 9
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge
clock pulse, so the SDA line is stable low during the
high period of the clock pulse. When the master is
transmitting to the MAX7319, the MAX7319 generates
the acknowledge bit because the device is the recipient.
When the MAX7319 is transmitting to the master, the
master generates the acknowledge bit because the
master is the recipient.
MAX7319
I2C Port Expander with Eight Inputs and
Maskable Transition Detection
_______________________________________________________________________________________
9
SCL
SDA
tR
tF
tBUF
START
CONDITION
STOP
CONDITION
REPEATED START CONDITION
START CONDITION
tSU,STO
tHD,STA
tSU,STA
tHD,DAT
tSU,DAT
tLOW
tHIGH
tHD,STA
Figure 1. 2-Wire Serial-Interface Timing Details
SDA
SCL
START
CONDITION
STOP
CONDITION
SP
Figure 2. START and STOP Conditions
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 3. Bit Transfer
SCL
SDA BY
TRANSMITTER
CLOCK PULSE
FOR ACKNOWLEDGMENT
START
CONDITION
SDA BY
RECEIVER
12
89
S
Figure 4. Acknowledge
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