receives data through an I2<" />
參數(shù)資料
型號(hào): MAX7324AEG+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/20頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 8B 24QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
接口: I²C
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時(shí)鐘: 400kHz
電源電壓: 1.71 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-QSOP
包裝: 帶卷 (TR)
包括: POR
Serial Interface
Serial Addressing
The MAX7324 operates as a slave that sends and
receives data through an I2C interface. The interface
uses a serial-data line (SDA) and a serial-clock line (SCL)
to achieve bidirectional communication between mas-
ter(s) and slave(s). The master initiates all data transfers
to and from the MAX7324 and generates the SCL clock
that synchronizes the data transfer (Figure 1).
SDA operates as both an input and an open-drain out-
put. A pullup resistor, typically 4.7k, is required on
SDA. SCL operates only as an input. A pullup resistor,
typically 4.7k, is required on SCL if there are multiple
masters on the 2-wire interface, or if the master in a sin-
gle-master system has an open-drain SCL output.
Each transmission consists of a START condition sent
by a master, followed by the MAX7324’s 7-bit slave
address plus R/W bit, 1 or more data bytes, and finally
a STOP condition (Figure 2).
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, the master
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 2).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 3).
MAX7324
I2C Port Expander with Eight Push-Pull Outputs
and Eight Inputs
10
______________________________________________________________________________________
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 3. Bit Transfer
SCL
SDA
tR
tF
tBUF
START
CONDITION
STOP
CONDITION
REPEATED START CONDITION
START CONDITION
tSU,STO
tHD,STA
tSU,STA
tHD,DAT
tSU,DAT
tLOW
tHIGH
tHD,STA
Figure 1. 2-Wire Serial-Interface Timing Details
SDA
SCL
START
CONDITION
STOP
CONDITION
SP
Figure 2. START and STOP Conditions
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