I2C Port Expander with 8 Push-Pull and 8 Open-Drain I/Os 8 Maxim Integra" />
參數(shù)資料
型號(hào): MAX7325ATG+
廠商: Maxim Integrated Products
文件頁數(shù): 16/17頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 8B 24TQFN-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 75
接口: I²C
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時(shí)鐘: 400kHz
電源電壓: 1.71 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 24-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-TQFN-EP(4x4)
包裝: 管件
包括: POR
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
8
Maxim Integrated
connected to V+ or GND. This is important because the
address selection is used to determine the power-up
logic state and whether pullups are enabled. At power-
up, the I2C SDA and SCL bus interface lines are high
impedance at the inputs of every device (master or
slave) connected to the bus, including the MAX7325.
This is guaranteed as part of the I2C specification.
Therefore, when address inputs AD0 and AD2 are con-
nected to SDA or SCL during power-up, they appear to
be connected to V+.
The power-up logic uses AD0 to select the power-up
state and whether pullups are enabled for ports P0–P3,
and AD2 for ports P4–P7. The rule is that a logic-high,
SDA, or SCL connection selects the pullups and sets
the default logic state to high. A logic-low deselects the
pullups and sets the default logic state to low (Table 2).
The port configuration is correct on power-up for a
standard I2C configuration, where SDA or SCL are
pulled up to V+ by the external I2C pullup resistors.
There are circumstances where the assumption that
SDA = SCL = V+ on power-up is not true—for example,
in applications in which there is legitimate bus activity
during power-up. If SDA and SCL are terminated with
pullup resistors to a different supply voltage than the
MAX7325’s supply voltage, and if that pullup supply
rises later than the MAX7325’s supply, then SDA or
SCL may appear at power-up to be connected to GND.
In such applications, use the four address combina-
tions that are selected by connecting address inputs
AD0 and AD2 to V+ or GND (shown in bold in Tables 2
and 3). These selections are guaranteed to be correct
at power-up, independent of SDA and SCL behavior. If
one of the other 12 address combinations is used, an
unexpected combination of pullups might be asserted
until the first I2C transmission (to any device, not neces-
sarily the MAX7325) is put on the bus, and an unex-
pected combination of ports can initialize as logic-low
outputs instead of inputs or logic-high outputs.
PIN
CONNECTION
DEVICE ADDRESS
PORT POWER-UP DEFAULT
40k
INPUT PULLUPS ENABLED
AD2
AD0
A6
A5
A4
A3
A2
A1
A0
P7
P6P5P4P3
P2P1P0
P7
P6
P5
P4
P3
P2
P1
P0
SCL
GND
1
0
1
1110
000
YYYY
————
SCL
V+
1
0
1
1111
111
YYYY
SCL
1
0
1
0
1
1111
111
YYYY
SCL
SDA
1
0
1
1111
111
YYYY
SDA
GND
1
0
1
0
1
1110
000
YYYY
————
SDA
V+
1
0
1
0
1
1111
111
YYYY
SDA
SCL
1
0
1
0
1
1111
111
YYYY
SDA
1
0
1
1111
111
YYYY
GND
1
0
1
0
0000
000
————
GND
V+
1
0
1
0
1
0
0001
111
————
YYY
Y
GND
SCL
1
0
1
0
1
0
0001
111
————
YYYY
GND
SDA
1
0
1
0
1
0
0001
111
————
YYYY
V+
GND
1
0
1
0
1
1110
000
Y
————
V+
1
0
1
0
1
1111
111
Y
YYYY
Y
V+
SCL
1
0
1
0
1
1111
111
YYYY
V+
SDA
1
0
1
1111
111
YYYY
Table 2. MAX7325 Address Map for Ports P0–P7
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